Search

Jay C. Chang

Examiner (ID: 164, Phone: (571)272-6132 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2817
Total Applications
685
Issued Applications
519
Pending Applications
88
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20416903 [patent_doc_number] => 12500198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Quad flat no-lead (QFN) package with tie bars and direct contact interconnect build-up structure and method for making the same [patent_app_type] => utility [patent_app_number] => 19/064511 [patent_app_country] => US [patent_app_date] => 2025-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 8065 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19064511 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/064511
Quad flat no-lead (QFN) package with tie bars and direct contact interconnect build-up structure and method for making the same Feb 25, 2025 Issued
Array ( [id] => 20283911 [patent_doc_number] => 20250309153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Apparatus and Method for Mitigating Crosstalk in an Advanced Package [patent_app_type] => utility [patent_app_number] => 18/754504 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754504 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754504
Apparatus and Method for Mitigating Crosstalk in an Advanced Package Jun 25, 2024 Pending
Array ( [id] => 20455980 [patent_doc_number] => 12519042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Methods for manufacturing a semiconductor package and a semiconductor module [patent_app_type] => utility [patent_app_number] => 18/629215 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 59 [patent_no_of_words] => 7813 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629215
Methods for manufacturing a semiconductor package and a semiconductor module Apr 7, 2024 Issued
Array ( [id] => 20441553 [patent_doc_number] => 12512395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Chip packaging method and chip package unit [patent_app_type] => utility [patent_app_number] => 18/616275 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/616275
Chip packaging method and chip package unit Mar 25, 2024 Issued
Array ( [id] => 20509170 [patent_doc_number] => 12543462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Display substrate and display device [patent_app_type] => utility [patent_app_number] => 18/615509 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 27087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615509
DISPLAY SUBSTRATE AND DISPLAY DEVICE Mar 24, 2024 Issued
Array ( [id] => 19269474 [patent_doc_number] => 20240213178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SEMICONDUCTOR DEVICE HAVING TAPERED METAL COATED SIDEWALLS [patent_app_type] => utility [patent_app_number] => 18/595905 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595905
SEMICONDUCTOR DEVICE HAVING TAPERED METAL COATED SIDEWALLS Mar 4, 2024 Pending
Array ( [id] => 20496933 [patent_doc_number] => 12538827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 18/592523 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/592523
Semiconductor structure Feb 29, 2024 Issued
Array ( [id] => 19191389 [patent_doc_number] => 20240170302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SYSTEM AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/427769 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/427769
SYSTEM AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE STRUCTURE Jan 29, 2024 Pending
Array ( [id] => 19176197 [patent_doc_number] => 20240162171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => METHOD FOR FABRICATING DEVICE DIE [patent_app_type] => utility [patent_app_number] => 18/418318 [patent_app_country] => US [patent_app_date] => 2024-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418318
METHOD FOR FABRICATING DEVICE DIE Jan 20, 2024 Pending
Array ( [id] => 20111591 [patent_doc_number] => 12362327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Method of forming packages of stacked chips [patent_app_type] => utility [patent_app_number] => 18/413020 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413020 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413020
Method of forming packages of stacked chips Jan 14, 2024 Issued
Array ( [id] => 19239521 [patent_doc_number] => 20240196717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => Pixel configurations for high resolution OVJP printed OLED displays [patent_app_type] => utility [patent_app_number] => 18/405312 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405312 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/405312
Pixel configurations for high resolution OVJP printed OLED displays Jan 4, 2024 Pending
Array ( [id] => 20416902 [patent_doc_number] => 12500197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Encapsulant-defined land grid array (LGA) package and method for making the same [patent_app_type] => utility [patent_app_number] => 18/389741 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 5610 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389741 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389741
Encapsulant-defined land grid array (LGA) package and method for making the same Dec 18, 2023 Issued
Array ( [id] => 20132241 [patent_doc_number] => 12374559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Double-sided partial molded SiP module [patent_app_type] => utility [patent_app_number] => 18/543992 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/543992
Double-sided partial molded SiP module Dec 17, 2023 Issued
Array ( [id] => 19086401 [patent_doc_number] => 20240113202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => Low-K Gate Spacer and Methods for Forming the Same [patent_app_type] => utility [patent_app_number] => 18/526084 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526084 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526084
Low-K Gate Spacer and Methods for Forming the Same Nov 30, 2023 Pending
Array ( [id] => 19071081 [patent_doc_number] => 20240105507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/526643 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526643
Semiconductor memory device and manufacturing method thereof Nov 30, 2023 Issued
Array ( [id] => 19071216 [patent_doc_number] => 20240105642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/522259 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522259
PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME Nov 28, 2023 Pending
Array ( [id] => 19038247 [patent_doc_number] => 20240088062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/518456 [patent_app_country] => US [patent_app_date] => 2023-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518456
PACKAGE STRUCTURE Nov 22, 2023 Pending
Array ( [id] => 20441560 [patent_doc_number] => 12512402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Chip-last wafer-level fan-out with optical fiber alignment structure [patent_app_type] => utility [patent_app_number] => 18/515078 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 41 [patent_no_of_words] => 6659 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515078
Chip-last wafer-level fan-out with optical fiber alignment structure Nov 19, 2023 Issued
Array ( [id] => 19038157 [patent_doc_number] => 20240087972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => EMBEDDED CHIP PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/389264 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389264
Embedded chip package and manufacturing method thereof Nov 13, 2023 Issued
Array ( [id] => 19038079 [patent_doc_number] => 20240087894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => HIGH DENSITY CARBON FILMS FOR PATTERNING APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/507328 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/507328
High density carbon films for patterning applications Nov 12, 2023 Issued
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