
Jay C. Chang
Examiner (ID: 1974, Phone: (571)272-6132 , Office: P/2895 )
| Most Active Art Unit | 2895 |
| Art Unit(s) | 2817, 2895 |
| Total Applications | 718 |
| Issued Applications | 535 |
| Pending Applications | 93 |
| Abandoned Applications | 101 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16629905
[patent_doc_number] => 20210048558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => TUNABLE HYPERBOLIC METAMATERIALS
[patent_app_type] => utility
[patent_app_number] => 16/541876
[patent_app_country] => US
[patent_app_date] => 2019-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5235
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541876
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/541876 | Tunable hyperbolic metamaterials | Aug 14, 2019 | Issued |
Array
(
[id] => 15217841
[patent_doc_number] => 20190371607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-05
[patent_title] => APPARATUS AND METHOD FOR BONDING SUBSTRATES
[patent_app_type] => utility
[patent_app_number] => 16/540133
[patent_app_country] => US
[patent_app_date] => 2019-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8174
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540133
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/540133 | Apparatus and method for bonding substrates | Aug 13, 2019 | Issued |
Array
(
[id] => 16631867
[patent_doc_number] => 20210050521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/539932
[patent_app_country] => US
[patent_app_date] => 2019-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12815
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539932
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/539932 | Techniques for forming self-aligned memory structures | Aug 12, 2019 | Issued |
Array
(
[id] => 15184893
[patent_doc_number] => 20190363038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => LDMOS Transistor and Method
[patent_app_type] => utility
[patent_app_number] => 16/535237
[patent_app_country] => US
[patent_app_date] => 2019-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8322
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16535237
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/535237 | LDMOS transistor and method | Aug 7, 2019 | Issued |
Array
(
[id] => 16624876
[patent_doc_number] => 20210043529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-11
[patent_title] => Protection Layer for Panel Handling Systems
[patent_app_type] => utility
[patent_app_number] => 16/534459
[patent_app_country] => US
[patent_app_date] => 2019-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10479
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534459
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/534459 | Protection layer for panel handling systems | Aug 6, 2019 | Issued |
Array
(
[id] => 18623833
[patent_doc_number] => 11756889
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making
[patent_app_type] => utility
[patent_app_number] => 16/534027
[patent_app_country] => US
[patent_app_date] => 2019-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 11327
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534027
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/534027 | Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making | Aug 6, 2019 | Issued |
Array
(
[id] => 16896251
[patent_doc_number] => 11037813
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-15
[patent_title] => Wafer processing method
[patent_app_type] => utility
[patent_app_number] => 16/531341
[patent_app_country] => US
[patent_app_date] => 2019-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 8322
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531341
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/531341 | Wafer processing method | Aug 4, 2019 | Issued |
Array
(
[id] => 15045817
[patent_doc_number] => 20190333913
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/504314
[patent_app_country] => US
[patent_app_date] => 2019-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2841
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16504314
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/504314 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Jul 6, 2019 | Abandoned |
Array
(
[id] => 16544902
[patent_doc_number] => 20200411317
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => INTEGRATED CIRCUIT PACKAGE ASSEMBLIES WITH HIGH-ASPECT RATIO METALLIZATION FEATURES
[patent_app_type] => utility
[patent_app_number] => 16/453895
[patent_app_country] => US
[patent_app_date] => 2019-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8919
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453895
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/453895 | INTEGRATED CIRCUIT PACKAGE ASSEMBLIES WITH HIGH-ASPECT RATIO METALLIZATION FEATURES | Jun 25, 2019 | Abandoned |
Array
(
[id] => 14938319
[patent_doc_number] => 20190304798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => METHODS FOR CYCLIC ETCHING OF A PATTERNED LAYER
[patent_app_type] => utility
[patent_app_number] => 16/446070
[patent_app_country] => US
[patent_app_date] => 2019-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6474
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446070
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/446070 | Methods for cyclic etching of a patterned layer | Jun 18, 2019 | Issued |
Array
(
[id] => 18071657
[patent_doc_number] => 11530483
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Substrate processing system
[patent_app_type] => utility
[patent_app_number] => 16/445096
[patent_app_country] => US
[patent_app_date] => 2019-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6940
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16445096
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/445096 | Substrate processing system | Jun 17, 2019 | Issued |
Array
(
[id] => 16386596
[patent_doc_number] => 10811441
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-20
[patent_title] => Pixel array substrate
[patent_app_type] => utility
[patent_app_number] => 16/441024
[patent_app_country] => US
[patent_app_date] => 2019-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5936
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441024
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/441024 | Pixel array substrate | Jun 13, 2019 | Issued |
Array
(
[id] => 15807921
[patent_doc_number] => 20200127103
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-23
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/441540
[patent_app_country] => US
[patent_app_date] => 2019-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7366
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441540
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/441540 | SEMICONDUCTOR DEVICE | Jun 13, 2019 | Abandoned |
Array
(
[id] => 16700093
[patent_doc_number] => 10950704
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-16
[patent_title] => Vertical memory devices
[patent_app_type] => utility
[patent_app_number] => 16/441644
[patent_app_country] => US
[patent_app_date] => 2019-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 65
[patent_figures_cnt] => 65
[patent_no_of_words] => 13734
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441644
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/441644 | Vertical memory devices | Jun 13, 2019 | Issued |
Array
(
[id] => 17063274
[patent_doc_number] => 11107887
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-31
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/441366
[patent_app_country] => US
[patent_app_date] => 2019-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2541
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441366
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/441366 | Semiconductor device | Jun 13, 2019 | Issued |
Array
(
[id] => 15718213
[patent_doc_number] => 20200105874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => BACK SIDE DOPANT ACTIVATION IN FIELD STOP IGBT
[patent_app_type] => utility
[patent_app_number] => 16/440696
[patent_app_country] => US
[patent_app_date] => 2019-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7112
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -33
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440696
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/440696 | BACK SIDE DOPANT ACTIVATION IN FIELD STOP IGBT | Jun 12, 2019 | Abandoned |
Array
(
[id] => 17908598
[patent_doc_number] => 11462460
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-04
[patent_title] => Electrical module assembly with embedded dies
[patent_app_type] => utility
[patent_app_number] => 16/433099
[patent_app_country] => US
[patent_app_date] => 2019-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3710
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16433099
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/433099 | Electrical module assembly with embedded dies | Jun 5, 2019 | Issued |
Array
(
[id] => 16315198
[patent_doc_number] => 20200293936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-17
[patent_title] => PHASE ESTIMATION WITH RANDOMIZED HAMILTONIANS
[patent_app_type] => utility
[patent_app_number] => 16/430205
[patent_app_country] => US
[patent_app_date] => 2019-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15907
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430205
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/430205 | Phase estimation with randomized hamiltonians | Jun 2, 2019 | Issued |
Array
(
[id] => 18688399
[patent_doc_number] => 11784143
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-10
[patent_title] => Single metal cavity antenna in package connected to an integrated transceiver front-end
[patent_app_type] => utility
[patent_app_number] => 16/421315
[patent_app_country] => US
[patent_app_date] => 2019-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 15110
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421315
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/421315 | Single metal cavity antenna in package connected to an integrated transceiver front-end | May 22, 2019 | Issued |
Array
(
[id] => 14785215
[patent_doc_number] => 20190267505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => CONTACTS FOR SOLAR CELLS
[patent_app_type] => utility
[patent_app_number] => 16/408268
[patent_app_country] => US
[patent_app_date] => 2019-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3342
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408268
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/408268 | Contacts for solar cells | May 8, 2019 | Issued |