Search

Jay C. Chang

Examiner (ID: 164, Phone: (571)272-6132 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2817
Total Applications
685
Issued Applications
519
Pending Applications
88
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14413855 [patent_doc_number] => 20190172771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => LDMOS Transistor [patent_app_type] => utility [patent_app_number] => 16/272545 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272545 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/272545
LDMOS transistor Feb 10, 2019 Issued
Array ( [id] => 15442631 [patent_doc_number] => 20200035499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/250180 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7884 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250180 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250180
Method of manufacturing semiconductor device Jan 16, 2019 Issued
Array ( [id] => 16653337 [patent_doc_number] => 10930530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Methods and apparatus for wafer temperature measurement [patent_app_type] => utility [patent_app_number] => 16/249588 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249588
Methods and apparatus for wafer temperature measurement Jan 15, 2019 Issued
Array ( [id] => 17122078 [patent_doc_number] => 11133219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Method of processing a wafer [patent_app_type] => utility [patent_app_number] => 16/247895 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 21770 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247895
Method of processing a wafer Jan 14, 2019 Issued
Array ( [id] => 14587741 [patent_doc_number] => 20190221479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => MANUFACTURING PROCESS OF ELEMENT CHIP [patent_app_type] => utility [patent_app_number] => 16/246627 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16246627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/246627
Manufacturing process of element chip Jan 13, 2019 Issued
Array ( [id] => 16664928 [patent_doc_number] => 10934158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor device including a microelectromechanical structure and an associated integrated electronic circuit [patent_app_type] => utility [patent_app_number] => 16/240415 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 42 [patent_no_of_words] => 5360 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/240415
Semiconductor device including a microelectromechanical structure and an associated integrated electronic circuit Jan 3, 2019 Issued
Array ( [id] => 15260233 [patent_doc_number] => 20190378850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => VERTICAL MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/239809 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239809
VERTICAL MEMORY DEVICES Jan 3, 2019 Abandoned
Array ( [id] => 14691681 [patent_doc_number] => 20190244956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => REFERENCE VOLTAGE GENERATION DEVICE [patent_app_type] => utility [patent_app_number] => 16/240428 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/240428
Reference voltage generation device Jan 3, 2019 Issued
Array ( [id] => 16593996 [patent_doc_number] => 10903273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Phase change memory with gradual conductance change [patent_app_type] => utility [patent_app_number] => 16/240233 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5501 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240233 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/240233
Phase change memory with gradual conductance change Jan 3, 2019 Issued
Array ( [id] => 16707693 [patent_doc_number] => 10957637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Quad flat no-lead package with wettable flanges [patent_app_type] => utility [patent_app_number] => 16/239400 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2461 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239400 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239400
Quad flat no-lead package with wettable flanges Jan 2, 2019 Issued
Array ( [id] => 15673473 [patent_doc_number] => 10600980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-24 [patent_title] => Quantum dot light-emitting diode (LED) with roughened electrode [patent_app_type] => utility [patent_app_number] => 16/223774 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7760 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223774 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223774
Quantum dot light-emitting diode (LED) with roughened electrode Dec 17, 2018 Issued
Array ( [id] => 14191545 [patent_doc_number] => 20190115478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/214197 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214197 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214197
Semiconductor device and manufacturing method thereof Dec 9, 2018 Issued
Array ( [id] => 14138167 [patent_doc_number] => 20190103473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => Contact Plugs and Methods Forming Same [patent_app_type] => utility [patent_app_number] => 16/206071 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/206071
Contact plugs and methods forming same Nov 29, 2018 Issued
Array ( [id] => 16308955 [patent_doc_number] => 10777766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Organic light-emitting diode display device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/206124 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 46 [patent_no_of_words] => 27598 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/206124
Organic light-emitting diode display device and method of fabricating the same Nov 29, 2018 Issued
Array ( [id] => 16448405 [patent_doc_number] => 10840336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods [patent_app_type] => utility [patent_app_number] => 16/192897 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 8491 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192897
Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods Nov 15, 2018 Issued
Array ( [id] => 15939353 [patent_doc_number] => 20200161310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => INTEGRATED CIRCUIT WITH VERTICAL STRUCTURES ON NODES OF A GRID [patent_app_type] => utility [patent_app_number] => 16/192905 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192905 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192905
Integrated circuit with vertical structures on nodes of a grid Nov 15, 2018 Issued
Array ( [id] => 15939355 [patent_doc_number] => 20200161311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => MICROELECTRONIC DEVICE WITH A MEMORY ELEMENT UTILIZING STACKED VERTICAL DEVICES [patent_app_type] => utility [patent_app_number] => 16/192963 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10988 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192963
Microelectronic device with a memory element utilizing stacked vertical devices Nov 15, 2018 Issued
Array ( [id] => 16448406 [patent_doc_number] => 10840337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Method for making a FINFET having reduced contact resistance [patent_app_type] => utility [patent_app_number] => 16/192911 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 8523 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192911
Method for making a FINFET having reduced contact resistance Nov 15, 2018 Issued
Array ( [id] => 15857261 [patent_doc_number] => 10643927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Ring isolated through-substrate vias for high resistivity substrates [patent_app_type] => utility [patent_app_number] => 16/192999 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 7770 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192999
Ring isolated through-substrate vias for high resistivity substrates Nov 15, 2018 Issued
Array ( [id] => 14382441 [patent_doc_number] => 20190165133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/192566 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192566 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192566
Method for forming semiconductor device Nov 14, 2018 Issued
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