Search

Jay C. Chang

Examiner (ID: 164, Phone: (571)272-6132 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2817
Total Applications
685
Issued Applications
519
Pending Applications
88
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12615348 [patent_doc_number] => 20180096946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SEMICONDUCTOR PACKAGES HAVING A FIDUCIAL MARKER AND METHODS FOR ALIGNING TOOLS RELATIVE TO THE FIDUCIAL MARKER [patent_app_type] => utility [patent_app_number] => 15/282754 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282754 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/282754
SEMICONDUCTOR PACKAGES HAVING A FIDUCIAL MARKER AND METHODS FOR ALIGNING TOOLS RELATIVE TO THE FIDUCIAL MARKER Sep 29, 2016 Abandoned
Array ( [id] => 12615816 [patent_doc_number] => 20180097102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/283149 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283149 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/283149
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Sep 29, 2016 Abandoned
Array ( [id] => 12615162 [patent_doc_number] => 20180096884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => LOCAL TRAP-RICH ISOLATION [patent_app_type] => utility [patent_app_number] => 15/281418 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281418
Local trap-rich isolation Sep 29, 2016 Issued
Array ( [id] => 11959583 [patent_doc_number] => 20170263735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'Method of Manufacturing Thin Film Transistor (TFT) and TFT' [patent_app_type] => utility [patent_app_number] => 15/282270 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3354 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15282270 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/282270
Method of Manufacturing Thin Film Transistor (TFT) and TFT Sep 29, 2016 Abandoned
Array ( [id] => 11397976 [patent_doc_number] => 20170018513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'SEMICONDUCTOR PACKAGE INCLUDING AN ANTENNA FORMED IN A GROOVE WITHIN A SEALING ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/277156 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5908 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277156 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277156
SEMICONDUCTOR PACKAGE INCLUDING AN ANTENNA FORMED IN A GROOVE WITHIN A SEALING ELEMENT Sep 26, 2016 Abandoned
Array ( [id] => 11385918 [patent_doc_number] => 20170011974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'SUBSTRATE PROCESSING APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/273875 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10509 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273875 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273875
SUBSTRATE PROCESSING APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM Sep 22, 2016 Abandoned
Array ( [id] => 12668893 [patent_doc_number] => 20180114797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => ARRAY SUBSTRATE AND METHOD FOR MAINTAINING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/503076 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15503076 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/503076
Array substrate and method for maintaining the same, display panel and display device Sep 13, 2016 Issued
Array ( [id] => 11911374 [patent_doc_number] => 09780196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method of forming a semiconductor device including forming a shield conductor overlying a gate conductor' [patent_app_type] => utility [patent_app_number] => 15/261308 [patent_app_country] => US [patent_app_date] => 2016-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11369 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15261308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/261308
Method of forming a semiconductor device including forming a shield conductor overlying a gate conductor Sep 8, 2016 Issued
Array ( [id] => 15109031 [patent_doc_number] => 10475847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Semiconductor device having stress-neutralized film stack and method of fabricating same [patent_app_type] => utility [patent_app_number] => 15/231390 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/231390
Semiconductor device having stress-neutralized film stack and method of fabricating same Aug 7, 2016 Issued
Array ( [id] => 11460124 [patent_doc_number] => 20170054029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/231061 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 63794 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231061 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/231061
Manufacturing method of semiconductor device Aug 7, 2016 Issued
Array ( [id] => 12181783 [patent_doc_number] => 20180040719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFET' [patent_app_type] => utility [patent_app_number] => 15/230871 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/230871
Parasitic capacitance reducing contact structure in a finFET Aug 7, 2016 Issued
Array ( [id] => 11439138 [patent_doc_number] => 20170040159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'SELF-LIMITING AND SATURATING CHEMICAL VAPOR DEPOSITION OF A SILICON BILAYER AND ALD' [patent_app_type] => utility [patent_app_number] => 15/230218 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15230218 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/230218
Self-limiting and saturating chemical vapor deposition of a silicon bilayer and ALD Aug 4, 2016 Issued
Array ( [id] => 11273726 [patent_doc_number] => 20160336272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'Semiconductor Device Having Gold Metallization Structures' [patent_app_type] => utility [patent_app_number] => 15/220161 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4788 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220161 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/220161
Semiconductor Device Having Gold Metallization Structures Jul 25, 2016 Abandoned
Array ( [id] => 11132271 [patent_doc_number] => 20160329247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/217032 [patent_app_country] => US [patent_app_date] => 2016-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15217032 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/217032
Method of manufacturing semiconductor device by applying molding layer in substrate groove Jul 21, 2016 Issued
Array ( [id] => 11111135 [patent_doc_number] => 20160308105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'LAMINATED ELECTRICAL TRACE WITHIN AN LED INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 15/195907 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4541 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/195907
LAMINATED ELECTRICAL TRACE WITHIN AN LED INTERCONNECT Jun 27, 2016 Abandoned
Array ( [id] => 11386084 [patent_doc_number] => 20170012139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/193564 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 45064 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193564 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/193564
Semiconductor device including transistor having low parasitic capacitance Jun 26, 2016 Issued
Array ( [id] => 13724061 [patent_doc_number] => 20170372986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => LDMOS Transistor and Method [patent_app_type] => utility [patent_app_number] => 15/192283 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192283
LDMOS transistor and method Jun 23, 2016 Issued
Array ( [id] => 13724061 [patent_doc_number] => 20170372986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => LDMOS Transistor and Method [patent_app_type] => utility [patent_app_number] => 15/192283 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192283
LDMOS transistor and method Jun 23, 2016 Issued
Array ( [id] => 14094039 [patent_doc_number] => 10242932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => LDMOS transistor and method [patent_app_type] => utility [patent_app_number] => 15/191989 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7368 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191989 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/191989
LDMOS transistor and method Jun 23, 2016 Issued
Array ( [id] => 13057475 [patent_doc_number] => 10050139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Semiconductor device including a LDMOS transistor and method [patent_app_type] => utility [patent_app_number] => 15/191937 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 8630 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/191937
Semiconductor device including a LDMOS transistor and method Jun 23, 2016 Issued
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