Search

Jay C. Chang

Examiner (ID: 164, Phone: (571)272-6132 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2817
Total Applications
685
Issued Applications
519
Pending Applications
88
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13724061 [patent_doc_number] => 20170372986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => LDMOS Transistor and Method [patent_app_type] => utility [patent_app_number] => 15/192283 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192283
LDMOS transistor and method Jun 23, 2016 Issued
Array ( [id] => 13723993 [patent_doc_number] => 20170372952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => SUBSTRATE AND METHOD INCLUDING FORMING A VIA COMPRISING A CONDUCTIVE LINER LAYER AND CONDUCTIVE PLUG HAVING DIFFERENT MICROSTRUCTURES [patent_app_type] => utility [patent_app_number] => 15/192146 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192146 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192146
Substrate and method including forming a via comprising a conductive liner layer and conductive plug having different microstructures Jun 23, 2016 Issued
Array ( [id] => 13724061 [patent_doc_number] => 20170372986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => LDMOS Transistor and Method [patent_app_type] => utility [patent_app_number] => 15/192283 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192283 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192283
LDMOS transistor and method Jun 23, 2016 Issued
Array ( [id] => 11110914 [patent_doc_number] => 20160307885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'Semiconductor Device Including a Diode at Least Partly Arranged in a Trench' [patent_app_type] => utility [patent_app_number] => 15/189031 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7123 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189031 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/189031
Semiconductor device including a diode at least partly arranged in a trench Jun 21, 2016 Issued
Array ( [id] => 14348533 [patent_doc_number] => 20190156239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => FIDELITY ESTIMATION FOR QUANTUM COMPUTING SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/301863 [patent_app_country] => US [patent_app_date] => 2016-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16301863 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/301863
Fidelity estimation for quantum computing systems May 16, 2016 Issued
Array ( [id] => 11972778 [patent_doc_number] => 20170276932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'OPTICAL ELEMENT MODULE AND METHOD FOR PRODUCING OPTICAL ELEMENT MODULE' [patent_app_type] => utility [patent_app_number] => 15/508596 [patent_app_country] => US [patent_app_date] => 2016-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6550 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15508596 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/508596
OPTICAL ELEMENT MODULE AND METHOD FOR PRODUCING OPTICAL ELEMENT MODULE May 9, 2016 Abandoned
Array ( [id] => 15791723 [patent_doc_number] => 10629593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Formation of semiconductor device with resistors having different resistances [patent_app_type] => utility [patent_app_number] => 15/134272 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 4531 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/134272
Formation of semiconductor device with resistors having different resistances Apr 19, 2016 Issued
Array ( [id] => 11981276 [patent_doc_number] => 20170285430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device' [patent_app_type] => utility [patent_app_number] => 15/508319 [patent_app_country] => US [patent_app_date] => 2016-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15508319 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/508319
Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device Mar 23, 2016 Abandoned
Array ( [id] => 11592726 [patent_doc_number] => 20170117138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'METHOD OF PREPARATION OF III-V COMPOUND LAYER ON LARGE AREA SI INSULATING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/067192 [patent_app_country] => US [patent_app_date] => 2016-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2445 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/067192
Method of preparation of III-V compound layer on large area Si insulating substrate Mar 10, 2016 Issued
Array ( [id] => 11439210 [patent_doc_number] => 20170040231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'METHOD FOR PROCESSING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 15/066667 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5601 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/066667
Method for processing substrate including forming a film on a silicon-containing surface of the substrate to prevent resist from extruding from the substrate during an imprinting process Mar 9, 2016 Issued
Array ( [id] => 11959302 [patent_doc_number] => 20170263454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'METHOD FOR FORMING FIN STRUCTURES FOR NON-PLANAR SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/067157 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5896 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067157 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/067157
Method for forming fin structures for non-planar semiconductor device Mar 9, 2016 Issued
Array ( [id] => 11502756 [patent_doc_number] => 20170076941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'SPIN COATING METHOD AND MANUFACTURING METHOD OF ELECTRONIC COMPONENT' [patent_app_type] => utility [patent_app_number] => 15/066815 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4411 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/066815
Spin coating method and manufacturing method of electronic component Mar 9, 2016 Issued
Array ( [id] => 11353587 [patent_doc_number] => 20160372328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/067163 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5371 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/067163
Method of manufacturing a silicon carbide semiconductor device including forming a protective film with a 2-layer structure comprised of silicon and carbon Mar 9, 2016 Issued
Array ( [id] => 11079182 [patent_doc_number] => 20160276147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'Silicon Nitride Film Forming Method and Silicon Nitride Film Forming Apparatus' [patent_app_type] => utility [patent_app_number] => 15/066494 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6197 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066494 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/066494
Silicon Nitride Film Forming Method and Silicon Nitride Film Forming Apparatus Mar 9, 2016 Abandoned
Array ( [id] => 12477831 [patent_doc_number] => 09991198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Layout method for compound semiconductor integrated circuits [patent_app_type] => utility [patent_app_number] => 15/066556 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 41 [patent_no_of_words] => 18016 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066556 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/066556
Layout method for compound semiconductor integrated circuits Mar 9, 2016 Issued
Array ( [id] => 11495651 [patent_doc_number] => 20170069836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/067098 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3055 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067098 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/067098
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING THE SAME Mar 9, 2016 Abandoned
Array ( [id] => 13271441 [patent_doc_number] => 10147807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Method of manufacturing pixel structure [patent_app_type] => utility [patent_app_number] => 15/065874 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3118 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/065874
Method of manufacturing pixel structure Mar 9, 2016 Issued
Array ( [id] => 11118195 [patent_doc_number] => 20160315169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/067115 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5409 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/067115
Method of manufacturing silicon carbide semiconductor device including forming an electric field control region by a laser doping technology Mar 9, 2016 Issued
Array ( [id] => 11911149 [patent_doc_number] => 09779968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method for processing semiconductor substrate and method for manufacturing semiconductor device in which said processing method is used' [patent_app_type] => utility [patent_app_number] => 15/063976 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 40 [patent_no_of_words] => 7989 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063976 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063976
Method for processing semiconductor substrate and method for manufacturing semiconductor device in which said processing method is used Mar 7, 2016 Issued
Array ( [id] => 10984202 [patent_doc_number] => 20160181147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/054696 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 19468 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15054696 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/054696
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Feb 25, 2016 Abandoned
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