
Jay C. Chang
Examiner (ID: 1974, Phone: (571)272-6132 , Office: P/2895 )
| Most Active Art Unit | 2895 |
| Art Unit(s) | 2817, 2895 |
| Total Applications | 718 |
| Issued Applications | 535 |
| Pending Applications | 93 |
| Abandoned Applications | 101 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 16637967
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[patent_issue_date] => 2021-02-09
[patent_title] => Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more EWLB packages per wafer with encapsulant deposited under temperature and pressure
[patent_app_type] => utility
[patent_app_number] => 13/937952
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Array
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[patent_title] => 'Semiconductor package including an antenna formed in a groove within a sealing element'
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Array
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[patent_title] => 'MONITORING A FIRST SYSTEM OF A TECHNICAL PLANT FOR PRODUCING A PRODUCT'
[patent_app_type] => utility
[patent_app_number] => 14/423209
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Array
(
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[patent_title] => 'Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and Pressure'
[patent_app_type] => utility
[patent_app_number] => 13/906060
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Array
(
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[patent_title] => 'Method of forming a transistor and structure therefor'
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Array
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[patent_title] => 'Removal of spurious microwave modes via flip-chip crossover'
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Array
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[patent_title] => 'IMAGE SENSOR WITH TRENCHED FILLER GRID'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/838156 | Image sensor with trenched filler grid within a dielectric grid including a reflective portion, a buffer and a high-K dielectric | Mar 14, 2013 | Issued |
Array
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[patent_title] => 'LIGHT EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING HEAT DISSIPATION SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/841858
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Array
(
[id] => 11201171
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[patent_title] => 'Electronic circuit having adjustable transistor device'
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[patent_app_number] => 13/837292
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/837292 | Electronic circuit having adjustable transistor device | Mar 14, 2013 | Issued |
Array
(
[id] => 9729162
[patent_doc_number] => 20140264869
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[patent_issue_date] => 2014-09-18
[patent_title] => 'Semiconductor Device'
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[patent_app_number] => 13/834806
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/834806 | Semiconductor Device | Mar 14, 2013 | Abandoned |
Array
(
[id] => 9729239
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[patent_issue_date] => 2014-09-18
[patent_title] => 'PACKAGE-ON-PACKAGE STRUCTURE WITH REDUCED HEIGHT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/833921 | Package-on-package structure with reduced height | Mar 14, 2013 | Issued |
Array
(
[id] => 11904442
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/838546 | III-nitride transistor with engineered substrate | Mar 14, 2013 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/841052 | Co-support circuit panel and microelectronic packages | Mar 14, 2013 | Issued |
Array
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[patent_title] => 'Forming Fence Conductors Using Spacer Pattern Transfer'
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/774682 | DRAM with a nanowire access transistor | Feb 21, 2013 | Issued |