Search

Jay C. Chang

Examiner (ID: 1974, Phone: (571)272-6132 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2817, 2895
Total Applications
718
Issued Applications
535
Pending Applications
93
Abandoned Applications
101

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16637967 [patent_doc_number] => 10916482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more EWLB packages per wafer with encapsulant deposited under temperature and pressure [patent_app_type] => utility [patent_app_number] => 13/937952 [patent_app_country] => US [patent_app_date] => 2013-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6810 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13937952 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/937952
Semiconductor device and method of forming reconstituted wafer with larger carrier to achieve more EWLB packages per wafer with encapsulant deposited under temperature and pressure Jul 8, 2013 Issued
Array ( [id] => 11279737 [patent_doc_number] => 09496219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Semiconductor package including an antenna formed in a groove within a sealing element' [patent_app_type] => utility [patent_app_number] => 13/935148 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5892 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935148
Semiconductor package including an antenna formed in a groove within a sealing element Jul 2, 2013 Issued
Array ( [id] => 10356868 [patent_doc_number] => 20150241873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'MONITORING A FIRST SYSTEM OF A TECHNICAL PLANT FOR PRODUCING A PRODUCT' [patent_app_type] => utility [patent_app_number] => 14/423209 [patent_app_country] => US [patent_app_date] => 2013-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8031 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14423209 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/423209
MONITORING A FIRST SYSTEM OF A TECHNICAL PLANT FOR PRODUCING A PRODUCT Jun 11, 2013 Abandoned
Array ( [id] => 9065167 [patent_doc_number] => 20130256923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and Pressure' [patent_app_type] => utility [patent_app_number] => 13/906060 [patent_app_country] => US [patent_app_date] => 2013-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6379 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13906060 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/906060
Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and Pressure May 29, 2013 Abandoned
Array ( [id] => 11240062 [patent_doc_number] => 09466708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Method of forming a transistor and structure therefor' [patent_app_type] => utility [patent_app_number] => 13/831883 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11297 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831883 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/831883
Method of forming a transistor and structure therefor Mar 14, 2013 Issued
Array ( [id] => 10189866 [patent_doc_number] => 09219298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Removal of spurious microwave modes via flip-chip crossover' [patent_app_type] => utility [patent_app_number] => 13/838324 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3857 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838324 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/838324
Removal of spurious microwave modes via flip-chip crossover Mar 14, 2013 Issued
Array ( [id] => 9728980 [patent_doc_number] => 20140264687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'IMAGE SENSOR WITH TRENCHED FILLER GRID' [patent_app_type] => utility [patent_app_number] => 13/838156 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838156 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/838156
Image sensor with trenched filler grid within a dielectric grid including a reflective portion, a buffer and a high-K dielectric Mar 14, 2013 Issued
Array ( [id] => 9600751 [patent_doc_number] => 20140197434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'LIGHT EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING HEAT DISSIPATION SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/841858 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2307 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/841858
LIGHT EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING HEAT DISSIPATION SUBSTRATE Mar 14, 2013 Abandoned
Array ( [id] => 11201171 [patent_doc_number] => 09431392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Electronic circuit having adjustable transistor device' [patent_app_type] => utility [patent_app_number] => 13/837292 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 13601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13837292 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/837292
Electronic circuit having adjustable transistor device Mar 14, 2013 Issued
Array ( [id] => 9729162 [patent_doc_number] => 20140264869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/834806 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1990 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834806 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/834806
Semiconductor Device Mar 14, 2013 Abandoned
Array ( [id] => 9729239 [patent_doc_number] => 20140264946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'PACKAGE-ON-PACKAGE STRUCTURE WITH REDUCED HEIGHT' [patent_app_type] => utility [patent_app_number] => 13/833921 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4524 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833921 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/833921
Package-on-package structure with reduced height Mar 14, 2013 Issued
Array ( [id] => 11904442 [patent_doc_number] => 09773884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'III-nitride transistor with engineered substrate' [patent_app_type] => utility [patent_app_number] => 13/838546 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2357 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838546 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/838546
III-nitride transistor with engineered substrate Mar 14, 2013 Issued
Array ( [id] => 9432926 [patent_doc_number] => 20140110832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'CO-SUPPORT CIRCUIT PANEL AND MICROELECTRONIC PACKAGES' [patent_app_type] => utility [patent_app_number] => 13/841052 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 35767 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841052 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/841052
Co-support circuit panel and microelectronic packages Mar 14, 2013 Issued
Array ( [id] => 9729179 [patent_doc_number] => 20140264886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Forming Fence Conductors Using Spacer Pattern Transfer' [patent_app_type] => utility [patent_app_number] => 13/835828 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4016 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835828 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835828
Forming Fence Conductors Using Spacer Pattern Transfer Mar 14, 2013 Abandoned
Array ( [id] => 9729210 [patent_doc_number] => 20140264917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'A Semiconductor Device with a Through-Silicon Via and a Method for Making the Same' [patent_app_type] => utility [patent_app_number] => 13/834061 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834061 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/834061
A Semiconductor Device with a Through-Silicon Via and a Method for Making the Same Mar 14, 2013 Abandoned
Array ( [id] => 11253221 [patent_doc_number] => 09478736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns' [patent_app_type] => utility [patent_app_number] => 13/835868 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 4419 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835868 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835868
Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns Mar 14, 2013 Issued
Array ( [id] => 9729175 [patent_doc_number] => 20140264882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Forming Fence Conductors Using Spacer Etched Trenches' [patent_app_type] => utility [patent_app_number] => 13/836647 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4557 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13836647 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/836647
Forming fence conductors using spacer etched trenches Mar 14, 2013 Issued
Array ( [id] => 9009998 [patent_doc_number] => 08525299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Electrical overstress protection using through-silicon-via (TSV)' [patent_app_type] => utility [patent_app_number] => 13/786646 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4758 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786646 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786646
Electrical overstress protection using through-silicon-via (TSV) Mar 5, 2013 Issued
Array ( [id] => 8989900 [patent_doc_number] => 20130217181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/775337 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5890 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775337 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775337
METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE Feb 24, 2013 Abandoned
Array ( [id] => 9191576 [patent_doc_number] => 20130330891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'DRAM WITH A NANOWIRE ACCESS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/774682 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774682
DRAM with a nanowire access transistor Feb 21, 2013 Issued
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