Search

Jay C. Chang

Examiner (ID: 1974, Phone: (571)272-6132 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2817, 2895
Total Applications
718
Issued Applications
535
Pending Applications
93
Abandoned Applications
101

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18865938 [patent_doc_number] => 20230420375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES [patent_app_type] => utility [patent_app_number] => 18/367285 [patent_app_country] => US [patent_app_date] => 2023-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18367285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/367285
Inorganic-based embedded-die layers for modular semiconductive devices Sep 11, 2023 Issued
Array ( [id] => 18860962 [patent_doc_number] => 20230415397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => CONDUIT INSERTS FOR ENCAPSULANT COMPOUND FORMULATION KNEADING AND ENCAPSULATION BACK-END ASSEMBLY PROCESSES [patent_app_type] => utility [patent_app_number] => 18/464409 [patent_app_country] => US [patent_app_date] => 2023-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18464409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/464409
Conduit inserts for encapsulant compound formulation kneading and encapsulation back-end assembly processes Sep 10, 2023 Issued
Array ( [id] => 19972488 [patent_doc_number] => 12341109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Chip package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/462414 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 43 [patent_no_of_words] => 3956 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462414 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/462414
Chip package and manufacturing method thereof Sep 6, 2023 Issued
Array ( [id] => 18821056 [patent_doc_number] => 20230395397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => CARRIER FILM DISPOSED ON A MOTHER SUBSTRATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/237115 [patent_app_country] => US [patent_app_date] => 2023-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18237115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/237115
Carrier film disposed on a mother substrate and method of manufacturing a semiconductor package Aug 22, 2023 Issued
Array ( [id] => 19806106 [patent_doc_number] => 20250072031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/453688 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453688
INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME Aug 21, 2023 Pending
Array ( [id] => 18812529 [patent_doc_number] => 20230386866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Semiconductor Package and Method of Forming Thereof [patent_app_type] => utility [patent_app_number] => 18/447428 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447428 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447428
Semiconductor package and method of forming thereof Aug 9, 2023 Issued
Array ( [id] => 18774322 [patent_doc_number] => 20230369153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => PACKAGES WITH ENLARGED THROUGH-VIAS IN ENCAPSULANT [patent_app_type] => utility [patent_app_number] => 18/361300 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361300
Packages with enlarged through-vias in encapsulant Jul 27, 2023 Issued
Array ( [id] => 20917062 [patent_doc_number] => 12713932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Semiconductor device and method of forming EMI shielding material in two-step process using light sintering [patent_app_type] => utility [patent_app_number] => 18/351687 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 44 [patent_no_of_words] => 1957 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351687
Semiconductor Device and Method of Forming EMI Shielding Material in Two-Step Process Using Light Sintering Jul 12, 2023 Pending
Array ( [id] => 19646625 [patent_doc_number] => 20240421145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => CIRCUIT LAYOUTS WITH STAGGERED GATE AND SOURCE/DRAIN REGIONS [patent_app_type] => utility [patent_app_number] => 18/333953 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333953 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333953
CIRCUIT LAYOUTS WITH STAGGERED GATE AND SOURCE/DRAIN REGIONS Jun 12, 2023 Pending
Array ( [id] => 19321478 [patent_doc_number] => 20240243025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => CHIP INTEGRATION INTO CAVITIES OF A HOST WAFER USING LATERAL DIELECTRIC MATERIAL BONDING [patent_app_type] => utility [patent_app_number] => 18/333449 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333449
Chip integration into cavities of a host wafer using lateral dielectric material bonding Jun 11, 2023 Issued
Array ( [id] => 19321479 [patent_doc_number] => 20240243026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => CHIP INTEGRATION INTO CAVITIES OF A HOST WAFER USING LATERAL DIELECTRIC MATERIAL BONDING [patent_app_type] => utility [patent_app_number] => 18/333460 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333460
Chip integration into cavities of a host wafer using lateral dielectric material bonding Jun 11, 2023 Issued
Array ( [id] => 19500352 [patent_doc_number] => 20240339370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Packaging of Dies Including TSVs using Sacrificial Carrier [patent_app_type] => utility [patent_app_number] => 18/329140 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/329140
Packaging of Dies Including TSVs using Sacrificial Carrier Jun 4, 2023 Pending
Array ( [id] => 19116423 [patent_doc_number] => 20240128173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/320456 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320456
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME May 18, 2023 Pending
Array ( [id] => 18631744 [patent_doc_number] => 20230290649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => METHOD OF MANUFACTURING AN INTERPOSER PRODUCT [patent_app_type] => utility [patent_app_number] => 18/320460 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320460
METHOD OF MANUFACTURING AN INTERPOSER PRODUCT May 18, 2023 Pending
Array ( [id] => 18833806 [patent_doc_number] => 20230402333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SYSTEM IN A PACKAGE (SIP) WITH AIR CAVITY AND EPOXY SEAL [patent_app_type] => utility [patent_app_number] => 18/197994 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197994
SYSTEM IN A PACKAGE (SIP) WITH AIR CAVITY AND EPOXY SEAL May 15, 2023 Pending
Array ( [id] => 18812615 [patent_doc_number] => 20230386952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => FAN-OUT WAFER-LEVEL PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/142412 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/142412
FAN-OUT WAFER-LEVEL PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING SAME May 1, 2023 Pending
Array ( [id] => 19305755 [patent_doc_number] => 20240234335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/310629 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310629
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF May 1, 2023 Pending
Array ( [id] => 19285813 [patent_doc_number] => 20240222290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/310815 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310815
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF May 1, 2023 Pending
Array ( [id] => 18570582 [patent_doc_number] => 20230260919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR PACKAGE AND ANTENNA MODULE COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 18/141568 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141568 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141568
Semiconductor package and antenna module comprising the same Apr 30, 2023 Issued
Array ( [id] => 19546425 [patent_doc_number] => 20240363461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Millimeter-Wave Passive Circuit Designs with Wafer-Level Chip-Scale Package [patent_app_type] => utility [patent_app_number] => 18/309277 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309277 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309277
Millimeter-Wave Passive Circuit Designs with Wafer-Level Chip-Scale Package Apr 27, 2023 Pending
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