Search

Jay C. Chang

Examiner (ID: 17046, Phone: (571)272-6132 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2817
Total Applications
698
Issued Applications
528
Pending Applications
84
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19919835 [patent_doc_number] => 12295231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Display panel, method for manufacturing same, and display terminal [patent_app_type] => utility [patent_app_number] => 17/622859 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17622859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/622859
Display panel, method for manufacturing same, and display terminal Dec 16, 2021 Issued
Array ( [id] => 18336325 [patent_doc_number] => 20230128274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => MICRO LIGHT EMITTING DIODE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/551185 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551185
Micro light emitting diode display device Dec 14, 2021 Issued
Array ( [id] => 17676892 [patent_doc_number] => 20220190059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => TRANSPARENT DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/550689 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550689
Transparent display device Dec 13, 2021 Issued
Array ( [id] => 18767015 [patent_doc_number] => 11817427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Semiconductor device having through silicon vias and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/545737 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7344 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545737
Semiconductor device having through silicon vias and manufacturing method thereof Dec 7, 2021 Issued
Array ( [id] => 19679461 [patent_doc_number] => 12191334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Semiconductor device with buffer layer and method of forming [patent_app_type] => utility [patent_app_number] => 17/536280 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536280
Semiconductor device with buffer layer and method of forming Nov 28, 2021 Issued
Array ( [id] => 17645334 [patent_doc_number] => 20220173073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => Chip Package and Method of Forming [patent_app_type] => utility [patent_app_number] => 17/535984 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535984
Chip package including stacked chips and chip couplers Nov 25, 2021 Issued
Array ( [id] => 17477670 [patent_doc_number] => 20220085174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING FRAME STRUCTURES LATERALLY SURROUNDING BACKSIDE METAL STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/532030 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532030
Method of manufacturing a semiconductor device having frame structures laterally surrounding backside metal structures Nov 21, 2021 Issued
Array ( [id] => 20649794 [patent_doc_number] => 12604758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Chip packaging apparatus and preparation method thereof [patent_app_type] => utility [patent_app_number] => 17/526966 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3481 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526966
Chip packaging apparatus and preparation method thereof Nov 14, 2021 Issued
Array ( [id] => 19597009 [patent_doc_number] => 12154863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Fan-out semiconductor package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/454742 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3159 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454742 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454742
Fan-out semiconductor package and method for manufacturing the same Nov 11, 2021 Issued
Array ( [id] => 18294711 [patent_doc_number] => 20230104397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => SEMICONDUCTOR PACKAGE SHIELDING STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/492493 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492493
Semiconductor package shielding structure Sep 30, 2021 Issued
Array ( [id] => 17373736 [patent_doc_number] => 20220028788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => INORGANIC-BASED EMBEDDED-DIE LAYERS FOR MODULAR SEMICONDUCTIVE DEVICES [patent_app_type] => utility [patent_app_number] => 17/492476 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492476
Inorganic-based embedded-die layers for modular semiconductive devices Sep 30, 2021 Issued
Array ( [id] => 19138035 [patent_doc_number] => 11973010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Chip packaging method and chip package unit [patent_app_type] => utility [patent_app_number] => 17/490038 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 2694 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/490038
Chip packaging method and chip package unit Sep 29, 2021 Issued
Array ( [id] => 19153769 [patent_doc_number] => 11978692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Semiconductor package, semiconductor module and methods for manufacturing a semiconductor package and a semiconductor module [patent_app_type] => utility [patent_app_number] => 17/471249 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 59 [patent_no_of_words] => 13695 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471249
Semiconductor package, semiconductor module and methods for manufacturing a semiconductor package and a semiconductor module Sep 9, 2021 Issued
Array ( [id] => 18935421 [patent_doc_number] => 11887863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Double-sided partial molded SIP module [patent_app_type] => utility [patent_app_number] => 17/447029 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 4631 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447029
Double-sided partial molded SIP module Sep 6, 2021 Issued
Array ( [id] => 17708706 [patent_doc_number] => 20220208714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => INTEGRATED CIRCUIT PACKAGE STRUCTURE, INTEGRATED CIRCUIT PACKAGE UNIT AND ASSOCIATED PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 17/468527 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468527 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468527
INTEGRATED CIRCUIT PACKAGE STRUCTURE, INTEGRATED CIRCUIT PACKAGE UNIT AND ASSOCIATED PACKAGING METHOD Sep 6, 2021 Abandoned
Array ( [id] => 18228924 [patent_doc_number] => 20230067918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => LEADFRAME-LESS LASER DIRECT STRUCTURING (LDS) PACKAGE [patent_app_type] => utility [patent_app_number] => 17/463140 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463140
Leadframe-less laser direct structuring (LDS) package Aug 30, 2021 Issued
Array ( [id] => 18229269 [patent_doc_number] => 20230068263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/460319 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460319
Semiconductor structure and method of forming the same Aug 29, 2021 Issued
Array ( [id] => 19858241 [patent_doc_number] => 12261092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/460346 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460346 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460346
Semiconductor package and manufacturing method thereof Aug 29, 2021 Issued
Array ( [id] => 19539467 [patent_doc_number] => 12132024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Semiconductor package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/460301 [patent_app_country] => US [patent_app_date] => 2021-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 38 [patent_no_of_words] => 20045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460301
Semiconductor package and method of manufacturing the same Aug 28, 2021 Issued
Array ( [id] => 18223152 [patent_doc_number] => 20230062146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Semiconductor Package and Method of Forming Thereof [patent_app_type] => utility [patent_app_number] => 17/458854 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458854
Semiconductor package and method of forming thereof Aug 26, 2021 Issued
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