Search

Jay Huang

Examiner (ID: 4119)

Most Active Art Unit
3685
Art Unit(s)
3685, 3619
Total Applications
545
Issued Applications
257
Pending Applications
70
Abandoned Applications
232

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6960455 [patent_doc_number] => 20010012221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'TIMING FUSE OPTION FOR ROW REPAIR' [patent_app_type] => new [patent_app_number] => 09/005815 [patent_app_country] => US [patent_app_date] => 1998-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012221.pdf [firstpage_image] =>[orig_patent_app_number] => 09005815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005815
Timing fuse option for row repair Jan 11, 1998 Issued
Array ( [id] => 4159526 [patent_doc_number] => 06064606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/001514 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 58 [patent_no_of_words] => 18197 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064606.pdf [firstpage_image] =>[orig_patent_app_number] => 001514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001514
Semiconductor integrated circuit device Dec 30, 1997 Issued
Array ( [id] => 4318151 [patent_doc_number] => 06252808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Semiconductor memory device having improved row redundancy scheme and method for curing defective cell' [patent_app_type] => 1 [patent_app_number] => 9/001712 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5569 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252808.pdf [firstpage_image] =>[orig_patent_app_number] => 001712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001712
Semiconductor memory device having improved row redundancy scheme and method for curing defective cell Dec 30, 1997 Issued
Array ( [id] => 4202191 [patent_doc_number] => 06130848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Circuit of reducing transmission delay for synchronous DRAM' [patent_app_type] => 1 [patent_app_number] => 8/988518 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1786 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130848.pdf [firstpage_image] =>[orig_patent_app_number] => 988518 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988518
Circuit of reducing transmission delay for synchronous DRAM Dec 9, 1997 Issued
Array ( [id] => 4425545 [patent_doc_number] => 06195282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Wide database architecture' [patent_app_type] => 1 [patent_app_number] => 8/986358 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2991 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195282.pdf [firstpage_image] =>[orig_patent_app_number] => 986358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986358
Wide database architecture Dec 7, 1997 Issued
Array ( [id] => 4038670 [patent_doc_number] => 05903508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Input buffer of memory device for reducing current consumption in standby mode' [patent_app_type] => 1 [patent_app_number] => 8/979227 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2474 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903508.pdf [firstpage_image] =>[orig_patent_app_number] => 979227 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979227
Input buffer of memory device for reducing current consumption in standby mode Nov 25, 1997 Issued
Array ( [id] => 4096213 [patent_doc_number] => 06018476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Nonvolatile configuration cells and cell arrays' [patent_app_type] => 1 [patent_app_number] => 8/972369 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11884 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018476.pdf [firstpage_image] =>[orig_patent_app_number] => 972369 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972369
Nonvolatile configuration cells and cell arrays Nov 17, 1997 Issued
Array ( [id] => 4250310 [patent_doc_number] => 06144578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Ferroelectric memory device and a method for manufacturing thereof' [patent_app_type] => 1 [patent_app_number] => 8/971915 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144578.pdf [firstpage_image] =>[orig_patent_app_number] => 971915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971915
Ferroelectric memory device and a method for manufacturing thereof Nov 16, 1997 Issued
Array ( [id] => 4185667 [patent_doc_number] => 06141278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Semiconductor memory device allowing fast successive selection of word lines in a test mode operation' [patent_app_type] => 1 [patent_app_number] => 8/966785 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 41 [patent_no_of_words] => 17341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141278.pdf [firstpage_image] =>[orig_patent_app_number] => 966785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966785
Semiconductor memory device allowing fast successive selection of word lines in a test mode operation Nov 9, 1997 Issued
Array ( [id] => 4170494 [patent_doc_number] => 06157587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Data sense arrangement for random access memory' [patent_app_type] => 1 [patent_app_number] => 8/965431 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2670 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157587.pdf [firstpage_image] =>[orig_patent_app_number] => 965431 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965431
Data sense arrangement for random access memory Nov 5, 1997 Issued
Array ( [id] => 4086376 [patent_doc_number] => 05966337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Method for overdriving bit line sense amplifier' [patent_app_type] => 1 [patent_app_number] => 8/958932 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 1433 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966337.pdf [firstpage_image] =>[orig_patent_app_number] => 958932 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958932
Method for overdriving bit line sense amplifier Oct 27, 1997 Issued
Array ( [id] => 3962265 [patent_doc_number] => 05999456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Flash EEPROM with controlled discharge time of the word lines and source potentials after erase' [patent_app_type] => 1 [patent_app_number] => 8/943391 [patent_app_country] => US [patent_app_date] => 1997-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8061 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999456.pdf [firstpage_image] =>[orig_patent_app_number] => 943391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/943391
Flash EEPROM with controlled discharge time of the word lines and source potentials after erase Oct 2, 1997 Issued
Array ( [id] => 3970902 [patent_doc_number] => 05901083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/939876 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5258 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901083.pdf [firstpage_image] =>[orig_patent_app_number] => 939876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939876
Nonvolatile semiconductor memory device Sep 28, 1997 Issued
Array ( [id] => 3809494 [patent_doc_number] => 05828620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'High voltage boosted word line supply charge pump and regulator for DRAM' [patent_app_type] => 1 [patent_app_number] => 8/921579 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3708 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828620.pdf [firstpage_image] =>[orig_patent_app_number] => 921579 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921579
High voltage boosted word line supply charge pump and regulator for DRAM Sep 1, 1997 Issued
Array ( [id] => 4045578 [patent_doc_number] => 05943254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes' [patent_app_type] => 1 [patent_app_number] => 8/919770 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 7683 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943254.pdf [firstpage_image] =>[orig_patent_app_number] => 919770 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919770
Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes Aug 27, 1997 Issued
Array ( [id] => 4131257 [patent_doc_number] => 06072728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Data output buffer' [patent_app_type] => 1 [patent_app_number] => 8/915394 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3240 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072728.pdf [firstpage_image] =>[orig_patent_app_number] => 915394 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915394
Data output buffer Aug 19, 1997 Issued
Array ( [id] => 4117259 [patent_doc_number] => 06101147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Semiconductor memory device equipped with column decoder outputting improved column selecting signals and control method of the same' [patent_app_type] => 1 [patent_app_number] => 8/894307 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5462 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101147.pdf [firstpage_image] =>[orig_patent_app_number] => 894307 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/894307
Semiconductor memory device equipped with column decoder outputting improved column selecting signals and control method of the same Aug 17, 1997 Issued
Array ( [id] => 3756816 [patent_doc_number] => 05802000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Highly integrated semiconductor device having stepwise bit lines' [patent_app_type] => 1 [patent_app_number] => 8/909782 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 2349 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802000.pdf [firstpage_image] =>[orig_patent_app_number] => 909782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/909782
Highly integrated semiconductor device having stepwise bit lines Aug 11, 1997 Issued
90/004716 MEMORY APPARATUS WITH RANDOM AND SEQUENTIAL ADDRESSING Aug 6, 1997 Issued
Array ( [id] => 4117276 [patent_doc_number] => 06101148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/907019 [patent_app_country] => US [patent_app_date] => 1997-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4681 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101148.pdf [firstpage_image] =>[orig_patent_app_number] => 907019 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/907019
Dynamic random access memory Aug 5, 1997 Issued
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