
Jay Huang
Examiner (ID: 4119)
| Most Active Art Unit | 3685 |
| Art Unit(s) | 3685, 3619 |
| Total Applications | 545 |
| Issued Applications | 257 |
| Pending Applications | 70 |
| Abandoned Applications | 232 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3932589
[patent_doc_number] => 05914900
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Circuits, systems and methods for modifying data stored in a memory using logic operations'
[patent_app_type] => 1
[patent_app_number] => 8/902674
[patent_app_country] => US
[patent_app_date] => 1997-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 7847
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/914/05914900.pdf
[firstpage_image] =>[orig_patent_app_number] => 902674
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/902674 | Circuits, systems and methods for modifying data stored in a memory using logic operations | Jul 29, 1997 | Issued |
Array
(
[id] => 3993881
[patent_doc_number] => 05910919
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Circuits, systems and methods for modifying data stored in a memory using logic operations'
[patent_app_type] => 1
[patent_app_number] => 8/903390
[patent_app_country] => US
[patent_app_date] => 1997-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 7848
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/910/05910919.pdf
[firstpage_image] =>[orig_patent_app_number] => 903390
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/903390 | Circuits, systems and methods for modifying data stored in a memory using logic operations | Jul 29, 1997 | Issued |
Array
(
[id] => 4015234
[patent_doc_number] => 05859806
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Semiconductor memory device and computer'
[patent_app_type] => 1
[patent_app_number] => 8/901938
[patent_app_country] => US
[patent_app_date] => 1997-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 45
[patent_no_of_words] => 31013
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/859/05859806.pdf
[firstpage_image] =>[orig_patent_app_number] => 901938
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/901938 | Semiconductor memory device and computer | Jul 28, 1997 | Issued |
Array
(
[id] => 3950838
[patent_doc_number] => 05930197
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/901771
[patent_app_country] => US
[patent_app_date] => 1997-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 28
[patent_no_of_words] => 10747
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930197.pdf
[firstpage_image] =>[orig_patent_app_number] => 901771
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/901771 | Semiconductor memory device | Jul 27, 1997 | Issued |
Array
(
[id] => 4202263
[patent_doc_number] => 06154398
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Low current redundancy anti-fuse method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/896702
[patent_app_country] => US
[patent_app_date] => 1997-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 5517
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/154/06154398.pdf
[firstpage_image] =>[orig_patent_app_number] => 896702
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/896702 | Low current redundancy anti-fuse method and apparatus | Jul 17, 1997 | Issued |
Array
(
[id] => 3904942
[patent_doc_number] => 05835411
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Computer including a fast sensing amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/895618
[patent_app_country] => US
[patent_app_date] => 1997-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 4206
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/835/05835411.pdf
[firstpage_image] =>[orig_patent_app_number] => 895618
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895618 | Computer including a fast sensing amplifier | Jul 16, 1997 | Issued |
Array
(
[id] => 4204814
[patent_doc_number] => 06044028
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Semiconductor storage device and electronic equipment using the same'
[patent_app_type] => 1
[patent_app_number] => 8/891822
[patent_app_country] => US
[patent_app_date] => 1997-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 15362
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 497
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/044/06044028.pdf
[firstpage_image] =>[orig_patent_app_number] => 891822
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/891822 | Semiconductor storage device and electronic equipment using the same | Jul 13, 1997 | Issued |
Array
(
[id] => 4093229
[patent_doc_number] => 06055173
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Circuit for programming antifuse bits'
[patent_app_type] => 1
[patent_app_number] => 8/891669
[patent_app_country] => US
[patent_app_date] => 1997-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4243
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/055/06055173.pdf
[firstpage_image] =>[orig_patent_app_number] => 891669
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/891669 | Circuit for programming antifuse bits | Jul 10, 1997 | Issued |
Array
(
[id] => 4011968
[patent_doc_number] => 05986931
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Low voltage single CMOS electrically erasable read-only memory'
[patent_app_type] => 1
[patent_app_number] => 8/890415
[patent_app_country] => US
[patent_app_date] => 1997-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 31
[patent_no_of_words] => 17406
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/986/05986931.pdf
[firstpage_image] =>[orig_patent_app_number] => 890415
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/890415 | Low voltage single CMOS electrically erasable read-only memory | Jul 8, 1997 | Issued |
Array
(
[id] => 4250410
[patent_doc_number] => 06144585
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Semiconductor storage device for storing three-or multi-valued data in one memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/890600
[patent_app_country] => US
[patent_app_date] => 1997-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6396
[patent_no_of_claims] => 65
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144585.pdf
[firstpage_image] =>[orig_patent_app_number] => 890600
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/890600 | Semiconductor storage device for storing three-or multi-valued data in one memory cell | Jul 8, 1997 | Issued |
Array
(
[id] => 4054519
[patent_doc_number] => 05875133
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'Semiconductor memory device and a method for stepping up its word lines'
[patent_app_type] => 1
[patent_app_number] => 8/809383
[patent_app_country] => US
[patent_app_date] => 1997-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 9861
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/875/05875133.pdf
[firstpage_image] =>[orig_patent_app_number] => 809383
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/809383 | Semiconductor memory device and a method for stepping up its word lines | Jun 18, 1997 | Issued |
Array
(
[id] => 3889468
[patent_doc_number] => 05825696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Semiconductor memory device including an SOI substrate'
[patent_app_type] => 1
[patent_app_number] => 8/876755
[patent_app_country] => US
[patent_app_date] => 1997-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 63
[patent_figures_cnt] => 94
[patent_no_of_words] => 23613
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825696.pdf
[firstpage_image] =>[orig_patent_app_number] => 876755
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/876755 | Semiconductor memory device including an SOI substrate | Jun 15, 1997 | Issued |
Array
(
[id] => 3963964
[patent_doc_number] => 05978272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Nonvolatile memory structure for programmable logic devices'
[patent_app_type] => 1
[patent_app_number] => 8/871589
[patent_app_country] => US
[patent_app_date] => 1997-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 3643
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/978/05978272.pdf
[firstpage_image] =>[orig_patent_app_number] => 871589
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/871589 | Nonvolatile memory structure for programmable logic devices | Jun 5, 1997 | Issued |
Array
(
[id] => 4064967
[patent_doc_number] => 05969991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Method of erasing a flash EEPROM memory cell array optimized for low power consumption'
[patent_app_type] => 1
[patent_app_number] => 8/867329
[patent_app_country] => US
[patent_app_date] => 1997-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9729
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 290
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/969/05969991.pdf
[firstpage_image] =>[orig_patent_app_number] => 867329
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867329 | Method of erasing a flash EEPROM memory cell array optimized for low power consumption | Jun 1, 1997 | Issued |
Array
(
[id] => 3913162
[patent_doc_number] => 05751653
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'DRAM with reduced leakage current'
[patent_app_type] => 1
[patent_app_number] => 8/867455
[patent_app_country] => US
[patent_app_date] => 1997-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1877
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751653.pdf
[firstpage_image] =>[orig_patent_app_number] => 867455
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867455 | DRAM with reduced leakage current | Jun 1, 1997 | Issued |
Array
(
[id] => 3957616
[patent_doc_number] => 05982699
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Parallel write logic for multi-port memory arrays'
[patent_app_type] => 1
[patent_app_number] => 8/858233
[patent_app_country] => US
[patent_app_date] => 1997-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9530
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/982/05982699.pdf
[firstpage_image] =>[orig_patent_app_number] => 858233
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/858233 | Parallel write logic for multi-port memory arrays | May 18, 1997 | Issued |
Array
(
[id] => 3940117
[patent_doc_number] => 05953256
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Reference voltage generator using flash memory cells'
[patent_app_type] => 1
[patent_app_number] => 8/853133
[patent_app_country] => US
[patent_app_date] => 1997-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3401
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/953/05953256.pdf
[firstpage_image] =>[orig_patent_app_number] => 853133
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/853133 | Reference voltage generator using flash memory cells | May 7, 1997 | Issued |
Array
(
[id] => 4027251
[patent_doc_number] => 05881004
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Burn-in stress control circuit for a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/850533
[patent_app_country] => US
[patent_app_date] => 1997-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3181
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/881/05881004.pdf
[firstpage_image] =>[orig_patent_app_number] => 850533
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850533 | Burn-in stress control circuit for a semiconductor memory device | May 1, 1997 | Issued |
Array
(
[id] => 1426160
[patent_doc_number] => 06510083
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-21
[patent_title] => 'Electrically erasable and programmable memory that allows data update without prior erasure of the memory'
[patent_app_type] => B1
[patent_app_number] => 08/850644
[patent_app_country] => US
[patent_app_date] => 1997-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5904
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/510/06510083.pdf
[firstpage_image] =>[orig_patent_app_number] => 08850644
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850644 | Electrically erasable and programmable memory that allows data update without prior erasure of the memory | May 1, 1997 | Issued |
Array
(
[id] => 3960417
[patent_doc_number] => 05991209
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Split sense amplifier and staging buffer for wide memory architecture'
[patent_app_type] => 1
[patent_app_number] => 8/827856
[patent_app_country] => US
[patent_app_date] => 1997-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4185
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 327
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/991/05991209.pdf
[firstpage_image] =>[orig_patent_app_number] => 827856
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/827856 | Split sense amplifier and staging buffer for wide memory architecture | Apr 10, 1997 | Issued |