Search

Jay Huang

Examiner (ID: 4119)

Most Active Art Unit
3685
Art Unit(s)
3685, 3619
Total Applications
545
Issued Applications
257
Pending Applications
70
Abandoned Applications
232

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3837711 [patent_doc_number] => 05784323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Test converage of embedded memories on semiconductor substrates' [patent_app_type] => 1 [patent_app_number] => 8/795367 [patent_app_country] => US [patent_app_date] => 1997-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 9007 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784323.pdf [firstpage_image] =>[orig_patent_app_number] => 795367 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/795367
Test converage of embedded memories on semiconductor substrates Feb 3, 1997 Issued
Array ( [id] => 3697164 [patent_doc_number] => 05696716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Programmable memory element' [patent_app_type] => 1 [patent_app_number] => 8/794965 [patent_app_country] => US [patent_app_date] => 1997-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2535 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696716.pdf [firstpage_image] =>[orig_patent_app_number] => 794965 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794965
Programmable memory element Feb 3, 1997 Issued
Array ( [id] => 3789285 [patent_doc_number] => 05808944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Semiconductor memory device having a defect relief arrangement' [patent_app_type] => 1 [patent_app_number] => 8/797654 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 11247 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808944.pdf [firstpage_image] =>[orig_patent_app_number] => 797654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797654
Semiconductor memory device having a defect relief arrangement Jan 30, 1997 Issued
Array ( [id] => 4017354 [patent_doc_number] => 06005795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Single ended dual port memory cell' [patent_app_type] => 1 [patent_app_number] => 8/789299 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5749 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005795.pdf [firstpage_image] =>[orig_patent_app_number] => 789299 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789299
Single ended dual port memory cell Jan 29, 1997 Issued
Array ( [id] => 4017368 [patent_doc_number] => 06005796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Single ended simpler dual port memory cell' [patent_app_type] => 1 [patent_app_number] => 8/789300 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5913 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005796.pdf [firstpage_image] =>[orig_patent_app_number] => 789300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789300
Single ended simpler dual port memory cell Jan 29, 1997 Issued
Array ( [id] => 3742099 [patent_doc_number] => 05694369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/790626 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6897 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 678 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694369.pdf [firstpage_image] =>[orig_patent_app_number] => 790626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/790626
Semiconductor memory device Jan 28, 1997 Issued
Array ( [id] => 4061304 [patent_doc_number] => 05870348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Dynamic semiconductor memory device having excellent charge retention characteristics' [patent_app_type] => 1 [patent_app_number] => 8/789240 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 71 [patent_no_of_words] => 33913 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870348.pdf [firstpage_image] =>[orig_patent_app_number] => 789240 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789240
Dynamic semiconductor memory device having excellent charge retention characteristics Jan 27, 1997 Issued
90/004531 DRAM CELL UTILIZING NOVEL CAPACITOR Jan 27, 1997 Issued
08/788556 STATIC RANDOM ACCESS MEMORY CELL UTILIZING DRIVE TRANSISTORS WITH LOW THRESHOLD VOLTAGE Jan 23, 1997 Abandoned
Array ( [id] => 3741891 [patent_doc_number] => 05694355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Memory cell and wordline driver for embedded DRAM in ASIC process' [patent_app_type] => 1 [patent_app_number] => 8/786922 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3711 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694355.pdf [firstpage_image] =>[orig_patent_app_number] => 786922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786922
Memory cell and wordline driver for embedded DRAM in ASIC process Jan 22, 1997 Issued
Array ( [id] => 3808021 [patent_doc_number] => 05781495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor memory device for multi-bit or multi-bank architectures' [patent_app_type] => 1 [patent_app_number] => 8/787483 [patent_app_country] => US [patent_app_date] => 1997-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 7041 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781495.pdf [firstpage_image] =>[orig_patent_app_number] => 787483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/787483
Semiconductor memory device for multi-bit or multi-bank architectures Jan 21, 1997 Issued
Array ( [id] => 3900755 [patent_doc_number] => 05777928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Multi-port register' [patent_app_type] => 1 [patent_app_number] => 8/785575 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7675 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777928.pdf [firstpage_image] =>[orig_patent_app_number] => 785575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785575
Multi-port register Jan 20, 1997 Issued
Array ( [id] => 3970844 [patent_doc_number] => 05901079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Skewed memory cell apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/782723 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4346 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901079.pdf [firstpage_image] =>[orig_patent_app_number] => 782723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/782723
Skewed memory cell apparatus and method Jan 12, 1997 Issued
Array ( [id] => 4010490 [patent_doc_number] => 05923585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Source biasing in non-volatile memory having row-based sectors' [patent_app_type] => 1 [patent_app_number] => 8/781741 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5387 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923585.pdf [firstpage_image] =>[orig_patent_app_number] => 781741 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781741
Source biasing in non-volatile memory having row-based sectors Jan 9, 1997 Issued
Array ( [id] => 3825338 [patent_doc_number] => 05812492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal' [patent_app_type] => 1 [patent_app_number] => 8/781013 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 12235 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812492.pdf [firstpage_image] =>[orig_patent_app_number] => 781013 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781013
Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal Jan 9, 1997 Issued
Array ( [id] => 4045715 [patent_doc_number] => 05943263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Apparatus and method for programming voltage protection in a non-volatile memory system' [patent_app_type] => 1 [patent_app_number] => 8/780624 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6793 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943263.pdf [firstpage_image] =>[orig_patent_app_number] => 780624 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/780624
Apparatus and method for programming voltage protection in a non-volatile memory system Jan 7, 1997 Issued
Array ( [id] => 3837738 [patent_doc_number] => 05784325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Semiconductor nonvolatile memory device' [patent_app_type] => 1 [patent_app_number] => 8/779115 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 6221 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784325.pdf [firstpage_image] =>[orig_patent_app_number] => 779115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779115
Semiconductor nonvolatile memory device Jan 5, 1997 Issued
Array ( [id] => 3830518 [patent_doc_number] => 05790455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Low voltage single supply CMOS electrically erasable read-only memory' [patent_app_type] => 1 [patent_app_number] => 8/778315 [patent_app_country] => US [patent_app_date] => 1997-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 10512 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790455.pdf [firstpage_image] =>[orig_patent_app_number] => 778315 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/778315
Low voltage single supply CMOS electrically erasable read-only memory Jan 1, 1997 Issued
Array ( [id] => 3825069 [patent_doc_number] => 05812469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method and apparatus for testing multi-port memory' [patent_app_type] => 1 [patent_app_number] => 8/775856 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3727 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812469.pdf [firstpage_image] =>[orig_patent_app_number] => 775856 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/775856
Method and apparatus for testing multi-port memory Dec 30, 1996 Issued
Array ( [id] => 3892689 [patent_doc_number] => 05748556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Tristatable driver for internal data bus lines' [patent_app_type] => 1 [patent_app_number] => 8/777836 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8012 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748556.pdf [firstpage_image] =>[orig_patent_app_number] => 777836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777836
Tristatable driver for internal data bus lines Dec 30, 1996 Issued
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