Jay Huang

Array ( [id] => 4086301 [patent_doc_number] => 05966332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Floating gate memory cell array allowing cell-by-cell erasure' [patent_app_type] => 1 [patent_app_number] => 8/774255 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 11681 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966332.pdf [firstpage_image] =>[orig_patent_app_number] => 774255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4012155 [patent_doc_number] => 05986943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Semiconductor memory device for shortening the set up time and hold time of control signals in synchronous DRAM' [patent_app_type] => 1 [patent_app_number] => 8/755553 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4748 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986943.pdf [firstpage_image] =>[orig_patent_app_number] => 755553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1496415 [patent_doc_number] => 06343030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Semiconductor device and pin arrangement' [patent_app_type] => B1 [patent_app_number] => 08/754758 [patent_app_country] => US [patent_app_date] => 1996-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3954 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343030.pdf [firstpage_image] =>[orig_patent_app_number] => 08754758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971235 [patent_doc_number] => 05901102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Semiconductor memory device achieving reduction in access time without increase in power consumption' [patent_app_type] => 1 [patent_app_number] => 8/746956 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 21429 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901102.pdf [firstpage_image] =>[orig_patent_app_number] => 746956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3888544 [patent_doc_number] => 05764561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Ferroelectric memory devices and method of using ferroelectric capacitors' [patent_app_type] => 1 [patent_app_number] => 8/749657 [patent_app_country] => US [patent_app_date] => 1996-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 11281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764561.pdf [firstpage_image] =>[orig_patent_app_number] => 749657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3825109 [patent_doc_number] => 05812473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Synchronous DRAM with alternated data line sensing' [patent_app_type] => 1 [patent_app_number] => 8/746655 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 1746 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812473.pdf [firstpage_image] =>[orig_patent_app_number] => 746655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3821553 [patent_doc_number] => 05831928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Semiconductor memory device including a plurality of dynamic memory cells connected in series' [patent_app_type] => 1 [patent_app_number] => 8/744455 [patent_app_country] => US [patent_app_date] => 1996-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831928.pdf [firstpage_image] =>[orig_patent_app_number] => 744455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3756789 [patent_doc_number] => 05801998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/740951 [patent_app_country] => US [patent_app_date] => 1996-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2103 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801998.pdf [firstpage_image] =>[orig_patent_app_number] => 740951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3807601 [patent_doc_number] => 05781466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Semiconductor memory with built-in cache' [patent_app_type] => 1 [patent_app_number] => 8/739970 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 18358 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781466.pdf [firstpage_image] =>[orig_patent_app_number] => 739970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836327 [patent_doc_number] => 05732042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Dram array with local latches' [patent_app_type] => 1 [patent_app_number] => 8/743953 [patent_app_country] => US [patent_app_date] => 1996-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5537 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/732/05732042.pdf [firstpage_image] =>[orig_patent_app_number] => 743953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3706646 [patent_doc_number] => 05677866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/739445 [patent_app_country] => US [patent_app_date] => 1996-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 4291 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677866.pdf [firstpage_image] =>[orig_patent_app_number] => 739445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054372 [patent_doc_number] => 05912837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Bitline disturb reduction' [patent_app_type] => 1 [patent_app_number] => 8/736858 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2811 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912837.pdf [firstpage_image] =>[orig_patent_app_number] => 736858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3732081 [patent_doc_number] => 05682355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Address transition detection (ATD) circuit' [patent_app_type] => 1 [patent_app_number] => 8/738541 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5331 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682355.pdf [firstpage_image] =>[orig_patent_app_number] => 738541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3852182 [patent_doc_number] => 05708623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Semiconductor memory decoder device' [patent_app_type] => 1 [patent_app_number] => 8/735655 [patent_app_country] => US [patent_app_date] => 1996-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4116 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708623.pdf [firstpage_image] =>[orig_patent_app_number] => 735655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853816 [patent_doc_number] => 05745415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Circuit for SRAM test mode isolated bitline modulation' [patent_app_type] => 1 [patent_app_number] => 8/734064 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2430 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745415.pdf [firstpage_image] =>[orig_patent_app_number] => 734064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873547 [patent_doc_number] => 05793667 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Sense amplifier control system for ferroelectric memories' [patent_app_type] => 1 [patent_app_number] => 8/733455 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3539 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793667.pdf [firstpage_image] =>[orig_patent_app_number] => 733455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873490 [patent_doc_number] => 05793663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Multiple page memory' [patent_app_type] => 1 [patent_app_number] => 8/733344 [patent_app_country] => US [patent_app_date] => 1996-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5945 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793663.pdf [firstpage_image] =>[orig_patent_app_number] => 733344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3789923 [patent_doc_number] => 05757692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/727852 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3828 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757692.pdf [firstpage_image] =>[orig_patent_app_number] => 727852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4116672 [patent_doc_number] => 06023441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method and apparatus for selectively enabling individual sets of registers in a row of a register array' [patent_app_type] => 1 [patent_app_number] => 8/726134 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3589 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023441.pdf [firstpage_image] =>[orig_patent_app_number] => 726134 [rel_patent_id] =>[rel_patent_doc_number] =>)