| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'Semiconductor memory device utilizing two data line pairs and realizing high-speed data readout'
[patent_app_type] => 1
[patent_app_number] => 8/667341
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Array
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[patent_doc_number] => 05553030
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Method and apparatus for controlling the output voltage provided by a charge pump circuit'
[patent_app_type] => 1
[patent_app_number] => 8/491792
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[patent_app_date] => 1996-06-19
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[firstpage_image] =>[orig_patent_app_number] => 491792
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/491792 | Method and apparatus for controlling the output voltage provided by a charge pump circuit | Jun 18, 1996 | Issued |
Array
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[patent_doc_number] => 05812443
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Memory integrated circuit and methods for manufacturing the same'
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[patent_app_number] => 8/662415
[patent_app_country] => US
[patent_app_date] => 1996-06-10
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[firstpage_image] =>[orig_patent_app_number] => 662415
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Array
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[id] => 4197548
[patent_doc_number] => 06151240
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Ferroelectric nonvolatile memory and oxide multi-layered structure'
[patent_app_type] => 1
[patent_app_number] => 8/655943
[patent_app_country] => US
[patent_app_date] => 1996-05-31
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 655943
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/655943 | Ferroelectric nonvolatile memory and oxide multi-layered structure | May 30, 1996 | Issued |
| 90/004255 | METHOD AND APPARATUS FOR INHIBITING A PREDECODER WHEN SELECTING A REDUNDANT ROW LINE | May 27, 1996 | Issued |
| 90/004254 | METHOD AND APPARATUS FOR INHIBITING A PREDECODER WHEN SELECTING A REDUNDANT ROW LINE | May 27, 1996 | Issued |
Array
(
[id] => 3912854
[patent_doc_number] => 05751633
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[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Method of screening hot temperature erase rejects at room temperature'
[patent_app_type] => 1
[patent_app_number] => 8/655357
[patent_app_country] => US
[patent_app_date] => 1996-05-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/655357 | Method of screening hot temperature erase rejects at room temperature | May 23, 1996 | Issued |
Array
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[id] => 3824749
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[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same'
[patent_app_type] => 1
[patent_app_number] => 8/644211
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[firstpage_image] =>[orig_patent_app_number] => 644211
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Array
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[id] => 3659296
[patent_doc_number] => 05606527
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Methods for detecting short-circuited signal lines in nonvolatile semiconductor memory and circuitry therefor'
[patent_app_type] => 1
[patent_app_number] => 8/639807
[patent_app_country] => US
[patent_app_date] => 1996-04-29
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[pdf_file] => patents/05/606/05606527.pdf
[firstpage_image] =>[orig_patent_app_number] => 639807
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/639807 | Methods for detecting short-circuited signal lines in nonvolatile semiconductor memory and circuitry therefor | Apr 28, 1996 | Issued |
Array
(
[id] => 3638851
[patent_doc_number] => 05687122
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Data output buffer'
[patent_app_type] => 1
[patent_app_number] => 8/638773
[patent_app_country] => US
[patent_app_date] => 1996-04-29
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[firstpage_image] =>[orig_patent_app_number] => 638773
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/638773 | Data output buffer | Apr 28, 1996 | Issued |
Array
(
[id] => 3826199
[patent_doc_number] => 05771198
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[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Source voltage generating circuit in semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 8/636115
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[firstpage_image] =>[orig_patent_app_number] => 636115
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636115 | Source voltage generating circuit in semiconductor memory | Apr 21, 1996 | Issued |
Array
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[id] => 3852012
[patent_doc_number] => 05708612
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/634252
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[patent_app_date] => 1996-04-18
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[firstpage_image] =>[orig_patent_app_number] => 634252
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/634252 | Semiconductor memory device | Apr 17, 1996 | Issued |
Array
(
[id] => 3799319
[patent_doc_number] => 05780891
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[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Nonvolatile floating gate memory with improved interploy dielectric'
[patent_app_type] => 1
[patent_app_number] => 8/634118
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[patent_app_date] => 1996-04-17
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[firstpage_image] =>[orig_patent_app_number] => 634118
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/634118 | Nonvolatile floating gate memory with improved interploy dielectric | Apr 16, 1996 | Issued |
Array
(
[id] => 3612997
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[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Semiconductor memory device having redundancy serial access memory portion'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/632280 | Semiconductor memory device having redundancy serial access memory portion | Apr 14, 1996 | Issued |
Array
(
[id] => 3971088
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[patent_issue_date] => 1999-05-04
[patent_title] => 'Circuit for designating an operating mode of a semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/631854 | Circuit for designating an operating mode of a semiconductor memory device | Apr 9, 1996 | Issued |
Array
(
[id] => 3873723
[patent_doc_number] => 05793678
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Parellel type nonvolatile semiconductor memory device method of using the same'
[patent_app_type] => 1
[patent_app_number] => 8/628817
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[patent_app_date] => 1996-04-05
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[firstpage_image] =>[orig_patent_app_number] => 628817
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/628817 | Parellel type nonvolatile semiconductor memory device method of using the same | Apr 4, 1996 | Issued |
| 08/625555 | SEMICONDUCTOR MEMORY DEVICE | Mar 31, 1996 | Abandoned |
Array
(
[id] => 3731955
[patent_doc_number] => 05682346
[patent_country] => US
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[patent_issue_date] => 1997-10-28
[patent_title] => 'Nonvolatile semiconductor memory device having suitable writing efficiency'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/626256 | Nonvolatile semiconductor memory device having suitable writing efficiency | Mar 28, 1996 | Issued |
Array
(
[id] => 3753246
[patent_doc_number] => 05754474
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Variable threshold voltage adjustment circuit for semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/619953
[patent_app_country] => US
[patent_app_date] => 1996-03-20
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/619953 | Variable threshold voltage adjustment circuit for semiconductor device | Mar 19, 1996 | Issued |
| 08/616211 | METHOD FOR CHECKING A SEMICONDUCTOR MEMORY DEVICE | Mar 14, 1996 | Abandoned |