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Jay Huang

Examiner (ID: 4119)

Most Active Art Unit
3685
Art Unit(s)
3685, 3619
Total Applications
545
Issued Applications
257
Pending Applications
70
Abandoned Applications
232

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3703517 [patent_doc_number] => 05650980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Semiconductor memory device utilizing two data line pairs and realizing high-speed data readout' [patent_app_type] => 1 [patent_app_number] => 8/667341 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 53 [patent_no_of_words] => 7891 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650980.pdf [firstpage_image] =>[orig_patent_app_number] => 667341 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/667341
Semiconductor memory device utilizing two data line pairs and realizing high-speed data readout Jun 19, 1996 Issued
Array ( [id] => 3596730 [patent_doc_number] => 05553030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Method and apparatus for controlling the output voltage provided by a charge pump circuit' [patent_app_type] => 1 [patent_app_number] => 8/491792 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6295 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553030.pdf [firstpage_image] =>[orig_patent_app_number] => 491792 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/491792
Method and apparatus for controlling the output voltage provided by a charge pump circuit Jun 18, 1996 Issued
Array ( [id] => 3824634 [patent_doc_number] => 05812443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Memory integrated circuit and methods for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/662415 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4648 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812443.pdf [firstpage_image] =>[orig_patent_app_number] => 662415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662415
Memory integrated circuit and methods for manufacturing the same Jun 9, 1996 Issued
Array ( [id] => 4197548 [patent_doc_number] => 06151240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Ferroelectric nonvolatile memory and oxide multi-layered structure' [patent_app_type] => 1 [patent_app_number] => 8/655943 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 11670 [patent_no_of_claims] => 104 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151240.pdf [firstpage_image] =>[orig_patent_app_number] => 655943 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655943
Ferroelectric nonvolatile memory and oxide multi-layered structure May 30, 1996 Issued
90/004255 METHOD AND APPARATUS FOR INHIBITING A PREDECODER WHEN SELECTING A REDUNDANT ROW LINE May 27, 1996 Issued
90/004254 METHOD AND APPARATUS FOR INHIBITING A PREDECODER WHEN SELECTING A REDUNDANT ROW LINE May 27, 1996 Issued
Array ( [id] => 3912854 [patent_doc_number] => 05751633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method of screening hot temperature erase rejects at room temperature' [patent_app_type] => 1 [patent_app_number] => 8/655357 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5076 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751633.pdf [firstpage_image] =>[orig_patent_app_number] => 655357 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655357
Method of screening hot temperature erase rejects at room temperature May 23, 1996 Issued
Array ( [id] => 3824749 [patent_doc_number] => 05812449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same' [patent_app_type] => 1 [patent_app_number] => 8/644211 [patent_app_country] => US [patent_app_date] => 1996-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 2639 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812449.pdf [firstpage_image] =>[orig_patent_app_number] => 644211 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/644211
Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same May 9, 1996 Issued
Array ( [id] => 3659296 [patent_doc_number] => 05606527 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Methods for detecting short-circuited signal lines in nonvolatile semiconductor memory and circuitry therefor' [patent_app_type] => 1 [patent_app_number] => 8/639807 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3821 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606527.pdf [firstpage_image] =>[orig_patent_app_number] => 639807 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639807
Methods for detecting short-circuited signal lines in nonvolatile semiconductor memory and circuitry therefor Apr 28, 1996 Issued
Array ( [id] => 3638851 [patent_doc_number] => 05687122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Data output buffer' [patent_app_type] => 1 [patent_app_number] => 8/638773 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687122.pdf [firstpage_image] =>[orig_patent_app_number] => 638773 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638773
Data output buffer Apr 28, 1996 Issued
Array ( [id] => 3826199 [patent_doc_number] => 05771198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Source voltage generating circuit in semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/636115 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2292 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771198.pdf [firstpage_image] =>[orig_patent_app_number] => 636115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636115
Source voltage generating circuit in semiconductor memory Apr 21, 1996 Issued
Array ( [id] => 3852012 [patent_doc_number] => 05708612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/634252 [patent_app_country] => US [patent_app_date] => 1996-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8118 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 549 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708612.pdf [firstpage_image] =>[orig_patent_app_number] => 634252 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634252
Semiconductor memory device Apr 17, 1996 Issued
Array ( [id] => 3799319 [patent_doc_number] => 05780891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Nonvolatile floating gate memory with improved interploy dielectric' [patent_app_type] => 1 [patent_app_number] => 8/634118 [patent_app_country] => US [patent_app_date] => 1996-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2472 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780891.pdf [firstpage_image] =>[orig_patent_app_number] => 634118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634118
Nonvolatile floating gate memory with improved interploy dielectric Apr 16, 1996 Issued
Array ( [id] => 3612997 [patent_doc_number] => 05579269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Semiconductor memory device having redundancy serial access memory portion' [patent_app_type] => 1 [patent_app_number] => 8/632280 [patent_app_country] => US [patent_app_date] => 1996-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4477 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579269.pdf [firstpage_image] =>[orig_patent_app_number] => 632280 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/632280
Semiconductor memory device having redundancy serial access memory portion Apr 14, 1996 Issued
Array ( [id] => 3971088 [patent_doc_number] => 05901094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Circuit for designating an operating mode of a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/631854 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5633 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901094.pdf [firstpage_image] =>[orig_patent_app_number] => 631854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/631854
Circuit for designating an operating mode of a semiconductor memory device Apr 9, 1996 Issued
Array ( [id] => 3873723 [patent_doc_number] => 05793678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Parellel type nonvolatile semiconductor memory device method of using the same' [patent_app_type] => 1 [patent_app_number] => 8/628817 [patent_app_country] => US [patent_app_date] => 1996-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6904 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 432 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793678.pdf [firstpage_image] =>[orig_patent_app_number] => 628817 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/628817
Parellel type nonvolatile semiconductor memory device method of using the same Apr 4, 1996 Issued
08/625555 SEMICONDUCTOR MEMORY DEVICE Mar 31, 1996 Abandoned
Array ( [id] => 3731955 [patent_doc_number] => 05682346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Nonvolatile semiconductor memory device having suitable writing efficiency' [patent_app_type] => 1 [patent_app_number] => 8/626256 [patent_app_country] => US [patent_app_date] => 1996-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7756 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682346.pdf [firstpage_image] =>[orig_patent_app_number] => 626256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626256
Nonvolatile semiconductor memory device having suitable writing efficiency Mar 28, 1996 Issued
Array ( [id] => 3753246 [patent_doc_number] => 05754474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Variable threshold voltage adjustment circuit for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/619953 [patent_app_country] => US [patent_app_date] => 1996-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3650 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754474.pdf [firstpage_image] =>[orig_patent_app_number] => 619953 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/619953
Variable threshold voltage adjustment circuit for semiconductor device Mar 19, 1996 Issued
08/616211 METHOD FOR CHECKING A SEMICONDUCTOR MEMORY DEVICE Mar 14, 1996 Abandoned
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