
Jay Huang
Examiner (ID: 4119)
| Most Active Art Unit | 3685 |
| Art Unit(s) | 3685, 3619 |
| Total Applications | 545 |
| Issued Applications | 257 |
| Pending Applications | 70 |
| Abandoned Applications | 232 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3666899
[patent_doc_number] => 05659512
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Semiconductor integrated circuit applicable to data read circuit from memory'
[patent_app_type] => 1
[patent_app_number] => 8/615364
[patent_app_country] => US
[patent_app_date] => 1996-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 5589
[patent_no_of_claims] => 115
[patent_no_of_ind_claims] => 31
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/659/05659512.pdf
[firstpage_image] =>[orig_patent_app_number] => 615364
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/615364 | Semiconductor integrated circuit applicable to data read circuit from memory | Mar 12, 1996 | Issued |
Array
(
[id] => 3798662
[patent_doc_number] => 05737275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Word line selection circuit for static random access memory'
[patent_app_type] => 1
[patent_app_number] => 8/614152
[patent_app_country] => US
[patent_app_date] => 1996-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 4287
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/737/05737275.pdf
[firstpage_image] =>[orig_patent_app_number] => 614152
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/614152 | Word line selection circuit for static random access memory | Mar 11, 1996 | Issued |
Array
(
[id] => 3803698
[patent_doc_number] => RE035750
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Wordline driver circuit having an automatic precharge circuit'
[patent_app_type] => 2
[patent_app_number] => 8/611618
[patent_app_country] => US
[patent_app_date] => 1996-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3722
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 28
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/035/RE035750.pdf
[firstpage_image] =>[orig_patent_app_number] => 611618
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/611618 | Wordline driver circuit having an automatic precharge circuit | Mar 7, 1996 | Issued |
Array
(
[id] => 3733153
[patent_doc_number] => 05673229
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-30
[patent_title] => 'Dynamic random access memory'
[patent_app_type] => 1
[patent_app_number] => 8/612759
[patent_app_country] => US
[patent_app_date] => 1996-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4679
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/673/05673229.pdf
[firstpage_image] =>[orig_patent_app_number] => 612759
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/612759 | Dynamic random access memory | Mar 7, 1996 | Issued |
Array
(
[id] => 3912997
[patent_doc_number] => 05751643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Dynamic memory word line driver'
[patent_app_type] => 1
[patent_app_number] => 8/611558
[patent_app_country] => US
[patent_app_date] => 1996-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 6211
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751643.pdf
[firstpage_image] =>[orig_patent_app_number] => 611558
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/611558 | Dynamic memory word line driver | Mar 5, 1996 | Issued |
Array
(
[id] => 4152802
[patent_doc_number] => 06061269
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'P-channel memory cell and method for forming the same'
[patent_app_type] => 1
[patent_app_number] => 8/613443
[patent_app_country] => US
[patent_app_date] => 1996-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2521
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/061/06061269.pdf
[firstpage_image] =>[orig_patent_app_number] => 613443
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/613443 | P-channel memory cell and method for forming the same | Mar 3, 1996 | Issued |
Array
(
[id] => 3967675
[patent_doc_number] => RE036180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Simultaneous read and refresh of different rows in a DRAM'
[patent_app_type] => 2
[patent_app_number] => 8/613455
[patent_app_country] => US
[patent_app_date] => 1996-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2768
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 24
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/036/RE036180.pdf
[firstpage_image] =>[orig_patent_app_number] => 613455
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/613455 | Simultaneous read and refresh of different rows in a DRAM | Feb 29, 1996 | Issued |
Array
(
[id] => 3501030
[patent_doc_number] => 05561636
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'Random access memory with a simple test arrangement'
[patent_app_type] => 1
[patent_app_number] => 8/613800
[patent_app_country] => US
[patent_app_date] => 1996-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5505
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/561/05561636.pdf
[firstpage_image] =>[orig_patent_app_number] => 613800
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/613800 | Random access memory with a simple test arrangement | Feb 29, 1996 | Issued |
Array
(
[id] => 3983321
[patent_doc_number] => RE036169
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 2
[patent_app_number] => 8/609097
[patent_app_country] => US
[patent_app_date] => 1996-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 7053
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 22
[patent_words_short_claim] => 261
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/036/RE036169.pdf
[firstpage_image] =>[orig_patent_app_number] => 609097
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/609097 | Semiconductor memory device | Feb 28, 1996 | Issued |
Array
(
[id] => 3713042
[patent_doc_number] => 05675548
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-07
[patent_title] => 'Semiconductor integrated circuit having logi gates'
[patent_app_type] => 1
[patent_app_number] => 8/608605
[patent_app_country] => US
[patent_app_date] => 1996-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 31
[patent_no_of_words] => 11200
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/675/05675548.pdf
[firstpage_image] =>[orig_patent_app_number] => 608605
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/608605 | Semiconductor integrated circuit having logi gates | Feb 28, 1996 | Issued |
Array
(
[id] => 3772545
[patent_doc_number] => 05742558
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Semiconductor memory device for plurality of ranges of power supply voltage'
[patent_app_type] => 1
[patent_app_number] => 8/608055
[patent_app_country] => US
[patent_app_date] => 1996-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 7872
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742558.pdf
[firstpage_image] =>[orig_patent_app_number] => 608055
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/608055 | Semiconductor memory device for plurality of ranges of power supply voltage | Feb 27, 1996 | Issued |
Array
(
[id] => 3809541
[patent_doc_number] => 05828623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Parallel write logic for multi-port memory arrays'
[patent_app_type] => 1
[patent_app_number] => 8/606115
[patent_app_country] => US
[patent_app_date] => 1996-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9528
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/828/05828623.pdf
[firstpage_image] =>[orig_patent_app_number] => 606115
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/606115 | Parallel write logic for multi-port memory arrays | Feb 22, 1996 | Issued |
Array
(
[id] => 3741018
[patent_doc_number] => 05666317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/605802
[patent_app_country] => US
[patent_app_date] => 1996-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 37
[patent_no_of_words] => 12818
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/666/05666317.pdf
[firstpage_image] =>[orig_patent_app_number] => 605802
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/605802 | Semiconductor memory device | Feb 22, 1996 | Issued |
| 08/605684 | NOVOLATILE SEMICONDUCTOR MEMORY DEVICE | Feb 21, 1996 | Abandoned |
Array
(
[id] => 3731970
[patent_doc_number] => 05682347
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-28
[patent_title] => 'Data reading method in semiconductor storage device capable of storing three-or multi-valued data in one memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/604447
[patent_app_country] => US
[patent_app_date] => 1996-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6394
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/682/05682347.pdf
[firstpage_image] =>[orig_patent_app_number] => 604447
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/604447 | Data reading method in semiconductor storage device capable of storing three-or multi-valued data in one memory cell | Feb 20, 1996 | Issued |
Array
(
[id] => 3845726
[patent_doc_number] => 05815450
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-29
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/601855
[patent_app_country] => US
[patent_app_date] => 1996-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4570
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/815/05815450.pdf
[firstpage_image] =>[orig_patent_app_number] => 601855
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/601855 | Semiconductor memory device | Feb 14, 1996 | Issued |
Array
(
[id] => 1599665
[patent_doc_number] => 06385088
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'Non-volatile memory device'
[patent_app_type] => B1
[patent_app_number] => 08/599857
[patent_app_country] => US
[patent_app_date] => 1996-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 48
[patent_no_of_words] => 9792
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/385/06385088.pdf
[firstpage_image] =>[orig_patent_app_number] => 08599857
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/599857 | Non-volatile memory device | Feb 12, 1996 | Issued |
Array
(
[id] => 4064906
[patent_doc_number] => 05969988
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Voltage multiplier circuit and nonvolatile semiconductor memory device having voltage multiplier'
[patent_app_type] => 1
[patent_app_number] => 8/598071
[patent_app_country] => US
[patent_app_date] => 1996-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 32
[patent_no_of_words] => 8121
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/969/05969988.pdf
[firstpage_image] =>[orig_patent_app_number] => 598071
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/598071 | Voltage multiplier circuit and nonvolatile semiconductor memory device having voltage multiplier | Feb 6, 1996 | Issued |
Array
(
[id] => 3897566
[patent_doc_number] => 05715188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Method and apparatus for parallel addressing of CAMs and RAMs'
[patent_app_type] => 1
[patent_app_number] => 8/597773
[patent_app_country] => US
[patent_app_date] => 1996-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 2691
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/715/05715188.pdf
[firstpage_image] =>[orig_patent_app_number] => 597773
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/597773 | Method and apparatus for parallel addressing of CAMs and RAMs | Feb 6, 1996 | Issued |
Array
(
[id] => 3736536
[patent_doc_number] => 05652729
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-29
[patent_title] => 'Semiconductor integrated circuit apparatus and method of adjusting refresh timer cycle'
[patent_app_type] => 1
[patent_app_number] => 8/597256
[patent_app_country] => US
[patent_app_date] => 1996-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 24
[patent_no_of_words] => 13680
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/652/05652729.pdf
[firstpage_image] =>[orig_patent_app_number] => 597256
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/597256 | Semiconductor integrated circuit apparatus and method of adjusting refresh timer cycle | Feb 5, 1996 | Issued |