Jay Huang

Array ( [id] => 3756577 [patent_doc_number] => 05801983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Semiconductor memory device having memory cells designed to offset bit line parasitic capacitance' [patent_app_type] => 1 [patent_app_number] => 8/590516 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3220 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801983.pdf [firstpage_image] =>[orig_patent_app_number] => 590516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3600324 [patent_doc_number] => 05586074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Semiconductor memory device with function of preventing loss of information due to leak of charges or disturbing' [patent_app_type] => 1 [patent_app_number] => 8/593270 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7952 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586074.pdf [firstpage_image] =>[orig_patent_app_number] => 593270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3757022 [patent_doc_number] => 05717652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Semiconductor memory device capable of high speed plural parallel test, method of data writing therefor and parallel tester' [patent_app_type] => 1 [patent_app_number] => 8/589358 [patent_app_country] => US [patent_app_date] => 1996-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 51 [patent_no_of_words] => 15917 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717652.pdf [firstpage_image] =>[orig_patent_app_number] => 589358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7644627 [patent_doc_number] => 06473346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Self burn-in circuit for semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 08/587746 [patent_app_country] => US [patent_app_date] => 1996-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 2566 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473346.pdf [firstpage_image] =>[orig_patent_app_number] => 08587746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3741399 [patent_doc_number] => 05636177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Static random access memory with improved noise immunity' [patent_app_type] => 1 [patent_app_number] => 8/587153 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2824 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636177.pdf [firstpage_image] =>[orig_patent_app_number] => 587153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3789112 [patent_doc_number] => 05808935 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Common source line driving circuit for use in nonvolatile semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 8/585311 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2732 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808935.pdf [firstpage_image] =>[orig_patent_app_number] => 585311 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3933295 [patent_doc_number] => 05877546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Semiconductor package with transparent window and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 8/581957 [patent_app_country] => US [patent_app_date] => 1996-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2010 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877546.pdf [firstpage_image] =>[orig_patent_app_number] => 581957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3790118 [patent_doc_number] => 05757706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Dynamic leaker for bit line refresh' [patent_app_type] => 1 [patent_app_number] => 8/581452 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3968 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757706.pdf [firstpage_image] =>[orig_patent_app_number] => 581452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3780784 [patent_doc_number] => 05734608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Residual charge elimination for a memory device' [patent_app_type] => 1 [patent_app_number] => 8/580549 [patent_app_country] => US [patent_app_date] => 1995-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3937 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/734/05734608.pdf [firstpage_image] =>[orig_patent_app_number] => 580549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3712913 [patent_doc_number] => 05675539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method and circuit for testing memories in integrated circuit form' [patent_app_type] => 1 [patent_app_number] => 8/575953 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3881 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675539.pdf [firstpage_image] =>[orig_patent_app_number] => 575953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3669417 [patent_doc_number] => 05592435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Pipelined read architecture for memory' [patent_app_type] => 1 [patent_app_number] => 8/575339 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7585 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592435.pdf [firstpage_image] =>[orig_patent_app_number] => 575339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3890045 [patent_doc_number] => 05729489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Programming flash memory using predictive learning methods' [patent_app_type] => 1 [patent_app_number] => 8/572757 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 7768 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729489.pdf [firstpage_image] =>[orig_patent_app_number] => 572757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3866457 [patent_doc_number] => RE035723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Synchronous burst-access memory' [patent_app_type] => 2 [patent_app_number] => 8/565958 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 10302 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 33 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035723.pdf [firstpage_image] =>[orig_patent_app_number] => 565958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3788086 [patent_doc_number] => 05821566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Surface emitting semiconductor laser device and fabricating method of the same' [patent_app_type] => 1 [patent_app_number] => 8/565170 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2239 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821566.pdf [firstpage_image] =>[orig_patent_app_number] => 565170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3712666 [patent_doc_number] => 05646894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Smart boost circuit for low voltage flash EPROM' [patent_app_type] => 1 [patent_app_number] => 8/560771 [patent_app_country] => US [patent_app_date] => 1995-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1298 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646894.pdf [firstpage_image] =>[orig_patent_app_number] => 560771 [rel_patent_id] =>[rel_patent_doc_number] =>)