| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_title] => 'Molded leadframe ball grid array'
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[patent_app_number] => 8/554688
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Array
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[patent_issue_date] => 1997-03-25
[patent_title] => 'Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors'
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Array
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[id] => 3816083
[patent_doc_number] => 05854767
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-29
[patent_title] => 'Semiconductor memory device having a plurality of blocks each including a parallel/serial conversion circuit'
[patent_app_type] => 1
[patent_app_number] => 8/548671
[patent_app_country] => US
[patent_app_date] => 1995-10-26
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[firstpage_image] =>[orig_patent_app_number] => 548671
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/548671 | Semiconductor memory device having a plurality of blocks each including a parallel/serial conversion circuit | Oct 25, 1995 | Issued |
| 08/546674 | MEMORY-CELL ARRAY AND A METHOD FOR REPAIRING THE SAME | Oct 22, 1995 | Abandoned |
Array
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[id] => 4037797
[patent_doc_number] => RE036061
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Integrated semiconductor memory'
[patent_app_type] => 2
[patent_app_number] => 8/542360
[patent_app_country] => US
[patent_app_date] => 1995-10-12
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Array
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[patent_issue_date] => 1997-07-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/540473 | Memory device having virtual ground line | Oct 9, 1995 | Issued |
Array
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[id] => 3671418
[patent_doc_number] => 05657267
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[patent_kind] => NA
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Array
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[id] => 3597872
[patent_doc_number] => 05550784
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[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Semiconductor memory device with synchronous dram whose speed grade is not limited'
[patent_app_type] => 1
[patent_app_number] => 8/534270
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[firstpage_image] =>[orig_patent_app_number] => 534270
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/534270 | Semiconductor memory device with synchronous dram whose speed grade is not limited | Sep 25, 1995 | Issued |
| 08/572830 | APPARATUS AND METHOD FOR READING MULT-LEVEL DATA STORED IN A SEMICONDUCTOR MEMORY | Sep 24, 1995 | Abandoned |
| 08/532451 | MULTICHIP SEMICONDUCTOR STRUCTURES WITH CONSOLIDATED CIRCUITRY AND PROGRAMMABLE ESD PROTECTION FOR INPUT OUTPUT NODES | Sep 21, 1995 | Abandoned |
Array
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[id] => 3526997
[patent_doc_number] => 05577002
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[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Semiconductor integrated circuit device implemented by bipolar and field effect transistors and having stable sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/528556
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/528556 | Semiconductor integrated circuit device implemented by bipolar and field effect transistors and having stable sense amplifier | Sep 14, 1995 | Issued |
Array
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[id] => 3741074
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[patent_issue_date] => 1997-09-09
[patent_title] => 'Synchronous DRAM memory with asynchronous column decode'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/522869 | Synchronous DRAM memory with asynchronous column decode | Aug 31, 1995 | Issued |
Array
(
[id] => 3537217
[patent_doc_number] => 05541874
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[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Semiconductor-integrated-circuit SRAM-cell array with single-ended current-sensing'
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Array
(
[id] => 3630965
[patent_doc_number] => 05689455
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[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'Circuit for programming antifuse bits'
[patent_app_type] => 1
[patent_app_number] => 8/522174
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/522174 | Circuit for programming antifuse bits | Aug 30, 1995 | Issued |
Array
(
[id] => 3520964
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[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/521455 | Timing reference circuit for bitline precharge in memory arrays | Aug 29, 1995 | Issued |
| 08/521170 | METHOD AND APPARATUS FOR SELECTIVELY ENABLING INDIVIDUAL SETS OF REGISTERS IN A ROW OF A REGISTER ARRAY | Aug 29, 1995 | Abandoned |
Array
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[id] => 3691366
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/516611 | Memory device with page select capability | Aug 17, 1995 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/515616 | Redundancy scheme for memory circuits | Aug 16, 1995 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1998-10-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/515904 | Dynamic memory word line driver scheme | Aug 15, 1995 | Issued |