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Jay Huang

Examiner (ID: 4119)

Most Active Art Unit
3685
Art Unit(s)
3685, 3619
Total Applications
545
Issued Applications
257
Pending Applications
70
Abandoned Applications
232

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3845421 [patent_doc_number] => 05847455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Molded leadframe ball grid array' [patent_app_type] => 1 [patent_app_number] => 8/554688 [patent_app_country] => US [patent_app_date] => 1995-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2011 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847455.pdf [firstpage_image] =>[orig_patent_app_number] => 554688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/554688
Molded leadframe ball grid array Nov 6, 1995 Issued
Array ( [id] => 3630440 [patent_doc_number] => 05615150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/551974 [patent_app_country] => US [patent_app_date] => 1995-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3104 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615150.pdf [firstpage_image] =>[orig_patent_app_number] => 551974 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/551974
Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors Nov 1, 1995 Issued
Array ( [id] => 3816083 [patent_doc_number] => 05854767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Semiconductor memory device having a plurality of blocks each including a parallel/serial conversion circuit' [patent_app_type] => 1 [patent_app_number] => 8/548671 [patent_app_country] => US [patent_app_date] => 1995-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 93 [patent_no_of_words] => 8394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854767.pdf [firstpage_image] =>[orig_patent_app_number] => 548671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/548671
Semiconductor memory device having a plurality of blocks each including a parallel/serial conversion circuit Oct 25, 1995 Issued
08/546674 MEMORY-CELL ARRAY AND A METHOD FOR REPAIRING THE SAME Oct 22, 1995 Abandoned
Array ( [id] => 4037797 [patent_doc_number] => RE036061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Integrated semiconductor memory' [patent_app_type] => 2 [patent_app_number] => 8/542360 [patent_app_country] => US [patent_app_date] => 1995-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5700 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036061.pdf [firstpage_image] =>[orig_patent_app_number] => 542360 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/542360
Integrated semiconductor memory Oct 11, 1995 Issued
Array ( [id] => 3703169 [patent_doc_number] => 05650959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Memory device having virtual ground line' [patent_app_type] => 1 [patent_app_number] => 8/540473 [patent_app_country] => US [patent_app_date] => 1995-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7787 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650959.pdf [firstpage_image] =>[orig_patent_app_number] => 540473 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540473
Memory device having virtual ground line Oct 9, 1995 Issued
Array ( [id] => 3671418 [patent_doc_number] => 05657267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Dynamic RAM (random access memory) with SEU (single event upset) detection' [patent_app_type] => 1 [patent_app_number] => 8/540604 [patent_app_country] => US [patent_app_date] => 1995-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 7898 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657267.pdf [firstpage_image] =>[orig_patent_app_number] => 540604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540604
Dynamic RAM (random access memory) with SEU (single event upset) detection Oct 4, 1995 Issued
Array ( [id] => 3597872 [patent_doc_number] => 05550784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Semiconductor memory device with synchronous dram whose speed grade is not limited' [patent_app_type] => 1 [patent_app_number] => 8/534270 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5342 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550784.pdf [firstpage_image] =>[orig_patent_app_number] => 534270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534270
Semiconductor memory device with synchronous dram whose speed grade is not limited Sep 25, 1995 Issued
08/572830 APPARATUS AND METHOD FOR READING MULT-LEVEL DATA STORED IN A SEMICONDUCTOR MEMORY Sep 24, 1995 Abandoned
08/532451 MULTICHIP SEMICONDUCTOR STRUCTURES WITH CONSOLIDATED CIRCUITRY AND PROGRAMMABLE ESD PROTECTION FOR INPUT OUTPUT NODES Sep 21, 1995 Abandoned
Array ( [id] => 3526997 [patent_doc_number] => 05577002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Semiconductor integrated circuit device implemented by bipolar and field effect transistors and having stable sense amplifier' [patent_app_type] => 1 [patent_app_number] => 8/528556 [patent_app_country] => US [patent_app_date] => 1995-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4865 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577002.pdf [firstpage_image] =>[orig_patent_app_number] => 528556 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/528556
Semiconductor integrated circuit device implemented by bipolar and field effect transistors and having stable sense amplifier Sep 14, 1995 Issued
Array ( [id] => 3741074 [patent_doc_number] => 05666321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Synchronous DRAM memory with asynchronous column decode' [patent_app_type] => 1 [patent_app_number] => 8/522869 [patent_app_country] => US [patent_app_date] => 1995-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4866 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666321.pdf [firstpage_image] =>[orig_patent_app_number] => 522869 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522869
Synchronous DRAM memory with asynchronous column decode Aug 31, 1995 Issued
Array ( [id] => 3537217 [patent_doc_number] => 05541874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Semiconductor-integrated-circuit SRAM-cell array with single-ended current-sensing' [patent_app_type] => 1 [patent_app_number] => 8/522796 [patent_app_country] => US [patent_app_date] => 1995-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3266 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541874.pdf [firstpage_image] =>[orig_patent_app_number] => 522796 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522796
Semiconductor-integrated-circuit SRAM-cell array with single-ended current-sensing Aug 31, 1995 Issued
Array ( [id] => 3630965 [patent_doc_number] => 05689455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Circuit for programming antifuse bits' [patent_app_type] => 1 [patent_app_number] => 8/522174 [patent_app_country] => US [patent_app_date] => 1995-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4250 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689455.pdf [firstpage_image] =>[orig_patent_app_number] => 522174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/522174
Circuit for programming antifuse bits Aug 30, 1995 Issued
Array ( [id] => 3520964 [patent_doc_number] => 05563831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Timing reference circuit for bitline precharge in memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/521455 [patent_app_country] => US [patent_app_date] => 1995-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3068 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563831.pdf [firstpage_image] =>[orig_patent_app_number] => 521455 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/521455
Timing reference circuit for bitline precharge in memory arrays Aug 29, 1995 Issued
08/521170 METHOD AND APPARATUS FOR SELECTIVELY ENABLING INDIVIDUAL SETS OF REGISTERS IN A ROW OF A REGISTER ARRAY Aug 29, 1995 Abandoned
Array ( [id] => 3691366 [patent_doc_number] => 05633828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Circuitry and methodology to test single bit failures of integrated circuit memory devices' [patent_app_type] => 1 [patent_app_number] => 8/519075 [patent_app_country] => US [patent_app_date] => 1995-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5724 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633828.pdf [firstpage_image] =>[orig_patent_app_number] => 519075 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519075
Circuitry and methodology to test single bit failures of integrated circuit memory devices Aug 23, 1995 Issued
Array ( [id] => 3636563 [patent_doc_number] => 05621692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Memory device with page select capability' [patent_app_type] => 1 [patent_app_number] => 8/516611 [patent_app_country] => US [patent_app_date] => 1995-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4116 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621692.pdf [firstpage_image] =>[orig_patent_app_number] => 516611 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/516611
Memory device with page select capability Aug 17, 1995 Issued
Array ( [id] => 3560816 [patent_doc_number] => 05572471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Redundancy scheme for memory circuits' [patent_app_type] => 1 [patent_app_number] => 8/515616 [patent_app_country] => US [patent_app_date] => 1995-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3642 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572471.pdf [firstpage_image] =>[orig_patent_app_number] => 515616 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/515616
Redundancy scheme for memory circuits Aug 16, 1995 Issued
Array ( [id] => 3798055 [patent_doc_number] => 05822253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Dynamic memory word line driver scheme' [patent_app_type] => 1 [patent_app_number] => 8/515904 [patent_app_country] => US [patent_app_date] => 1995-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1580 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822253.pdf [firstpage_image] =>[orig_patent_app_number] => 515904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/515904
Dynamic memory word line driver scheme Aug 15, 1995 Issued
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