Jay Huang

Array ( [id] => 3563610 [patent_doc_number] => 05519659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Semiconductor memory device having circuit for activating predetermined rows of memory cells upon detection of disturb refresh test' [patent_app_type] => 1 [patent_app_number] => 8/408256 [patent_app_country] => US [patent_app_date] => 1995-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 37 [patent_no_of_words] => 12849 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519659.pdf [firstpage_image] =>[orig_patent_app_number] => 408256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3644635 [patent_doc_number] => 05610859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/404572 [patent_app_country] => US [patent_app_date] => 1995-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 176 [patent_no_of_words] => 17556 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610859.pdf [firstpage_image] =>[orig_patent_app_number] => 404572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3558145 [patent_doc_number] => 05546349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Exchangeable hierarchical data line structure' [patent_app_type] => 1 [patent_app_number] => 8/403265 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 10106 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546349.pdf [firstpage_image] =>[orig_patent_app_number] => 403265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3520989 [patent_doc_number] => 05563833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Using one memory to supply addresses to an associated memory during testing' [patent_app_type] => 1 [patent_app_number] => 8/398465 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5296 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563833.pdf [firstpage_image] =>[orig_patent_app_number] => 398465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3623400 [patent_doc_number] => 05535164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'BIST tester for multiple memories' [patent_app_type] => 1 [patent_app_number] => 8/398468 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10022 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535164.pdf [firstpage_image] =>[orig_patent_app_number] => 398468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3873241 [patent_doc_number] => 05796653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Circuit for the selection of redundant memory elements and flash EEPROM memory comprising said circuit' [patent_app_type] => 1 [patent_app_number] => 8/394314 [patent_app_country] => US [patent_app_date] => 1995-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4676 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796653.pdf [firstpage_image] =>[orig_patent_app_number] => 394314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3608668 [patent_doc_number] => 05559744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Semiconductor integrated circuit device having a test mode setting circuit' [patent_app_type] => 1 [patent_app_number] => 8/389165 [patent_app_country] => US [patent_app_date] => 1995-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7131 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559744.pdf [firstpage_image] =>[orig_patent_app_number] => 389165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3736461 [patent_doc_number] => 05652724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Burst EDO memory device having pipelined output buffer' [patent_app_type] => 1 [patent_app_number] => 8/386563 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8279 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652724.pdf [firstpage_image] =>[orig_patent_app_number] => 386563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3602817 [patent_doc_number] => 05521864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Non-volatile semiconductor memory device allowing fast verifying operation' [patent_app_type] => 1 [patent_app_number] => 8/385866 [patent_app_country] => US [patent_app_date] => 1995-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 7687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521864.pdf [firstpage_image] =>[orig_patent_app_number] => 385866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3566305 [patent_doc_number] => 05544125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Semiconductor integrated circuit having logic gates' [patent_app_type] => 1 [patent_app_number] => 8/383866 [patent_app_country] => US [patent_app_date] => 1995-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 11207 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/544/05544125.pdf [firstpage_image] =>[orig_patent_app_number] => 383866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3623507 [patent_doc_number] => 05535171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Data output buffer of a semiconducter memory device' [patent_app_type] => 1 [patent_app_number] => 8/383767 [patent_app_country] => US [patent_app_date] => 1995-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2030 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535171.pdf [firstpage_image] =>[orig_patent_app_number] => 383767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3507536 [patent_doc_number] => 05532957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Field reconfigurable logic/memory array' [patent_app_type] => 1 [patent_app_number] => 8/381180 [patent_app_country] => US [patent_app_date] => 1995-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1673 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532957.pdf [firstpage_image] =>[orig_patent_app_number] => 381180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4384237 [patent_doc_number] => 06288941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks' [patent_app_type] => 1 [patent_app_number] => 8/379020 [patent_app_country] => US [patent_app_date] => 1995-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 12594 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288941.pdf [firstpage_image] =>[orig_patent_app_number] => 379020 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3582561 [patent_doc_number] => 05539698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Redundancy circuit device' [patent_app_type] => 1 [patent_app_number] => 8/378268 [patent_app_country] => US [patent_app_date] => 1995-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 7 [patent_no_of_words] => 7091 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539698.pdf [firstpage_image] =>[orig_patent_app_number] => 378268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3608818 [patent_doc_number] => 05559753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Apparatus and method for preventing bus contention during power-up in a computer system with two or more DRAM banks' [patent_app_type] => 1 [patent_app_number] => 8/378164 [patent_app_country] => US [patent_app_date] => 1995-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3437 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559753.pdf [firstpage_image] =>[orig_patent_app_number] => 378164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3699199 [patent_doc_number] => 05604708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Fail-safe system for preserving a backup battery' [patent_app_type] => 1 [patent_app_number] => 8/378169 [patent_app_country] => US [patent_app_date] => 1995-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3551 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604708.pdf [firstpage_image] =>[orig_patent_app_number] => 378169 [rel_patent_id] =>[rel_patent_doc_number] =>)