Search

Jay M Patidar

Examiner (ID: 7822, Phone: (571)272-2265 , Office: P/2858 )

Most Active Art Unit
2858
Art Unit(s)
2858, 2215, 2607, 2618, 2862
Total Applications
2477
Issued Applications
2063
Pending Applications
169
Abandoned Applications
244

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3744401 [patent_doc_number] => 05666556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit' [patent_app_type] => 1 [patent_app_number] => 8/710572 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2099 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666556.pdf [firstpage_image] =>[orig_patent_app_number] => 710572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710572
Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit Sep 18, 1996 Issued
Array ( [id] => 3705445 [patent_doc_number] => 05661800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Method and manufacture for preventing unauthorized use by judging the corresponding relationship between logical and physical addresses' [patent_app_type] => 1 [patent_app_number] => 8/672399 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 9795 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661800.pdf [firstpage_image] =>[orig_patent_app_number] => 672399 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672399
Method and manufacture for preventing unauthorized use by judging the corresponding relationship between logical and physical addresses Jun 27, 1996 Issued
Array ( [id] => 3701386 [patent_doc_number] => 05664154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'M/A for optimizing retry time upon cache-miss by selecting a delay time according to whether the addressed location\'s dirty bit indicates a write-back' [patent_app_type] => 1 [patent_app_number] => 8/537495 [patent_app_country] => US [patent_app_date] => 1995-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3526 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664154.pdf [firstpage_image] =>[orig_patent_app_number] => 537495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/537495
M/A for optimizing retry time upon cache-miss by selecting a delay time according to whether the addressed location's dirty bit indicates a write-back Oct 1, 1995 Issued
Array ( [id] => 3843607 [patent_doc_number] => 05712970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Method and apparatus for reliably storing data to be written to a peripheral device subsystem using plural controllers' [patent_app_type] => 1 [patent_app_number] => 8/535595 [patent_app_country] => US [patent_app_date] => 1995-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6072 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712970.pdf [firstpage_image] =>[orig_patent_app_number] => 535595 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/535595
Method and apparatus for reliably storing data to be written to a peripheral device subsystem using plural controllers Sep 27, 1995 Issued
Array ( [id] => 3660402 [patent_doc_number] => 05640535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Library apparatus for duplicating disks and then sorting them to easily distinguish defective disks from normally copied disks' [patent_app_type] => 1 [patent_app_number] => 8/530485 [patent_app_country] => US [patent_app_date] => 1995-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 9656 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640535.pdf [firstpage_image] =>[orig_patent_app_number] => 530485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/530485
Library apparatus for duplicating disks and then sorting them to easily distinguish defective disks from normally copied disks Sep 18, 1995 Issued
Array ( [id] => 3701294 [patent_doc_number] => 05664147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'System and method that progressively prefetches additional lines to a distributed stream buffer as the sequentiality of the memory accessing is demonstrated' [patent_app_type] => 1 [patent_app_number] => 8/519031 [patent_app_country] => US [patent_app_date] => 1995-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6468 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664147.pdf [firstpage_image] =>[orig_patent_app_number] => 519031 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/519031
System and method that progressively prefetches additional lines to a distributed stream buffer as the sequentiality of the memory accessing is demonstrated Aug 23, 1995 Issued
Array ( [id] => 3735939 [patent_doc_number] => 05701436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Information processing apparatus including synchronous storage having backup registers for storing the latest sets of information to enable state restoration after interruption' [patent_app_type] => 1 [patent_app_number] => 8/508685 [patent_app_country] => US [patent_app_date] => 1995-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8229 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701436.pdf [firstpage_image] =>[orig_patent_app_number] => 508685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/508685
Information processing apparatus including synchronous storage having backup registers for storing the latest sets of information to enable state restoration after interruption Jul 27, 1995 Issued
Array ( [id] => 3661446 [patent_doc_number] => 05640602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Transferring digital data in units of 2 bytes to increase utilization of a 2-byte-wide bus' [patent_app_type] => 1 [patent_app_number] => 8/486289 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7817 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640602.pdf [firstpage_image] =>[orig_patent_app_number] => 486289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/486289
Transferring digital data in units of 2 bytes to increase utilization of a 2-byte-wide bus Jun 6, 1995 Issued
Array ( [id] => 3739180 [patent_doc_number] => 05652906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Data driven processor with improved initialization functions because operation data shares address space with initialization data' [patent_app_type] => 1 [patent_app_number] => 8/465333 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 35 [patent_no_of_words] => 25333 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652906.pdf [firstpage_image] =>[orig_patent_app_number] => 465333 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/465333
Data driven processor with improved initialization functions because operation data shares address space with initialization data Jun 4, 1995 Issued
Array ( [id] => 3669657 [patent_doc_number] => 05659695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Method and apparatus utilizing simultaneous memory reads for increasing memory access bandwidth in a digital signal processor' [patent_app_type] => 1 [patent_app_number] => 8/459859 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4182 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659695.pdf [firstpage_image] =>[orig_patent_app_number] => 459859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/459859
Method and apparatus utilizing simultaneous memory reads for increasing memory access bandwidth in a digital signal processor Jun 1, 1995 Issued
Array ( [id] => 3642083 [patent_doc_number] => 05687340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Reduced area floating point processor control logic utilizing a decoder between a control unit and the FPU' [patent_app_type] => 1 [patent_app_number] => 8/442544 [patent_app_country] => US [patent_app_date] => 1995-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687340.pdf [firstpage_image] =>[orig_patent_app_number] => 442544 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/442544
Reduced area floating point processor control logic utilizing a decoder between a control unit and the FPU May 15, 1995 Issued
Array ( [id] => 3695644 [patent_doc_number] => 05634110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Cache coherency using flexible directory bit vectors' [patent_app_type] => 1 [patent_app_number] => 8/435463 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6035 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634110.pdf [firstpage_image] =>[orig_patent_app_number] => 435463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435463
Cache coherency using flexible directory bit vectors May 4, 1995 Issued
Array ( [id] => 3705935 [patent_doc_number] => 05651135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Multi-way set associative cache system in which the number of lines per set differs and loading depends on access frequency' [patent_app_type] => 1 [patent_app_number] => 8/413010 [patent_app_country] => US [patent_app_date] => 1995-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8023 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/651/05651135.pdf [firstpage_image] =>[orig_patent_app_number] => 413010 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/413010
Multi-way set associative cache system in which the number of lines per set differs and loading depends on access frequency Mar 28, 1995 Issued
Array ( [id] => 3734270 [patent_doc_number] => 05682496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Filtered serial event controlled command port for memory' [patent_app_type] => 1 [patent_app_number] => 8/386688 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2988 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682496.pdf [firstpage_image] =>[orig_patent_app_number] => 386688 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386688
Filtered serial event controlled command port for memory Feb 9, 1995 Issued
Array ( [id] => 3743808 [patent_doc_number] => 05666512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Disk array having hot spare resources and methods for using hot spare resources to store user data' [patent_app_type] => 1 [patent_app_number] => 8/386574 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666512.pdf [firstpage_image] =>[orig_patent_app_number] => 386574 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386574
Disk array having hot spare resources and methods for using hot spare resources to store user data Feb 9, 1995 Issued
Array ( [id] => 3705908 [patent_doc_number] => 05651133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Methods for avoiding over-commitment of virtual capacity in a redundant hierarchic data storage system' [patent_app_type] => 1 [patent_app_number] => 8/382350 [patent_app_country] => US [patent_app_date] => 1995-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9593 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/651/05651133.pdf [firstpage_image] =>[orig_patent_app_number] => 382350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/382350
Methods for avoiding over-commitment of virtual capacity in a redundant hierarchic data storage system Jan 31, 1995 Issued
Array ( [id] => 3695580 [patent_doc_number] => 05634106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Power saving system and method for refreshing a computer memory by switching between interval refresh and self-refresh operations' [patent_app_type] => 1 [patent_app_number] => 8/361680 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2719 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634106.pdf [firstpage_image] =>[orig_patent_app_number] => 361680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/361680
Power saving system and method for refreshing a computer memory by switching between interval refresh and self-refresh operations Dec 21, 1994 Issued
Array ( [id] => 3695453 [patent_doc_number] => 05634099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Direct memory access unit for transferring data between processor memories in multiprocessing systems' [patent_app_type] => 1 [patent_app_number] => 8/352953 [patent_app_country] => US [patent_app_date] => 1994-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7491 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 412 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634099.pdf [firstpage_image] =>[orig_patent_app_number] => 352953 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/352953
Direct memory access unit for transferring data between processor memories in multiprocessing systems Dec 8, 1994 Issued
Array ( [id] => 3669810 [patent_doc_number] => 05659704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Methods and system for reserving storage space for data migration in a redundant hierarchic data storage system by dynamically computing maximum storage space for mirror redundancy' [patent_app_type] => 1 [patent_app_number] => 8/348391 [patent_app_country] => US [patent_app_date] => 1994-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659704.pdf [firstpage_image] =>[orig_patent_app_number] => 348391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/348391
Methods and system for reserving storage space for data migration in a redundant hierarchic data storage system by dynamically computing maximum storage space for mirror redundancy Dec 1, 1994 Issued
Array ( [id] => 3633463 [patent_doc_number] => 05615352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Methods for adding storage disks to a hierarchic disk array while maintaining data availability' [patent_app_type] => 1 [patent_app_number] => 8/319385 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9485 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615352.pdf [firstpage_image] =>[orig_patent_app_number] => 319385 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/319385
Methods for adding storage disks to a hierarchic disk array while maintaining data availability Oct 4, 1994 Issued
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