Search

Jay W. Radke

Examiner (ID: 9961, Phone: (571)270-1622 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1108
Issued Applications
954
Pending Applications
63
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20182134 [patent_doc_number] => 20250266092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/975798 [patent_app_country] => US [patent_app_date] => 2024-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18975798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/975798
BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAME Dec 9, 2024 Pending
Array ( [id] => 20182134 [patent_doc_number] => 20250266092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/975798 [patent_app_country] => US [patent_app_date] => 2024-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18975798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/975798
BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAME Dec 9, 2024 Pending
Array ( [id] => 20352521 [patent_doc_number] => 20250349373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/783124 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783124
MEMORY DEVICE AND OPERATION METHOD THEREOF Jul 23, 2024 Pending
Array ( [id] => 19559631 [patent_doc_number] => 20240371423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/778659 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778659
CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES Jul 18, 2024 Pending
Array ( [id] => 19559631 [patent_doc_number] => 20240371423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/778659 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778659
CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES Jul 18, 2024 Pending
Array ( [id] => 20367083 [patent_doc_number] => 20250356895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MRAM CIRCUIT AND LAYOUT [patent_app_type] => utility [patent_app_number] => 18/752801 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752801
MRAM CIRCUIT AND LAYOUT Jun 24, 2024 Pending
Array ( [id] => 20367083 [patent_doc_number] => 20250356895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MRAM CIRCUIT AND LAYOUT [patent_app_type] => utility [patent_app_number] => 18/752801 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752801
MRAM CIRCUIT AND LAYOUT Jun 24, 2024 Pending
Array ( [id] => 19467657 [patent_doc_number] => 20240321327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PRE-DECODER CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/677609 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677609 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677609
PRE-DECODER CIRCUITRY May 28, 2024 Pending
Array ( [id] => 20229150 [patent_doc_number] => 12417804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Low power management for sleep mode operation of a memory device [patent_app_type] => utility [patent_app_number] => 18/675997 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675997
Low power management for sleep mode operation of a memory device May 27, 2024 Issued
Array ( [id] => 20229150 [patent_doc_number] => 12417804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Low power management for sleep mode operation of a memory device [patent_app_type] => utility [patent_app_number] => 18/675997 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675997
Low power management for sleep mode operation of a memory device May 27, 2024 Issued
Array ( [id] => 20088542 [patent_doc_number] => 20250218478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/669931 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669931
SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME May 20, 2024 Issued
Array ( [id] => 19435730 [patent_doc_number] => 20240304228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SYSTEMS AND METHODS FOR DUAL STANDBY MODES IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/668795 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668795
SYSTEMS AND METHODS FOR DUAL STANDBY MODES IN MEMORY May 19, 2024 Pending
Array ( [id] => 19917457 [patent_doc_number] => 12292826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Method for managing a memory apparatus [patent_app_type] => utility [patent_app_number] => 18/663114 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9173 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663114
Method for managing a memory apparatus May 13, 2024 Issued
Array ( [id] => 20352502 [patent_doc_number] => 20250349354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/658128 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658128
MEMORY DEVICE AND OPERATING METHOD THEREOF May 7, 2024 Pending
Array ( [id] => 20338746 [patent_doc_number] => 20250342866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => MEMORY WITH REDUCED LEAKAGE THROUGH ANALOG HEAD SWITCH CONTROL [patent_app_type] => utility [patent_app_number] => 18/653472 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653472
MEMORY WITH REDUCED LEAKAGE THROUGH ANALOG HEAD SWITCH CONTROL May 1, 2024 Pending
Array ( [id] => 20338762 [patent_doc_number] => 20250342882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => VOLTAGE CONTROL CIRCUITS AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/652963 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652963 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652963
VOLTAGE CONTROL CIRCUITS AND METHODS FOR OPERATING THE SAME May 1, 2024 Pending
Array ( [id] => 19972226 [patent_doc_number] => 12340844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Phase-change memory cell and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/632583 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 3809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632583
Phase-change memory cell and method for fabricating the same Apr 10, 2024 Issued
Array ( [id] => 19972226 [patent_doc_number] => 12340844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Phase-change memory cell and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/632583 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 3809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632583
Phase-change memory cell and method for fabricating the same Apr 10, 2024 Issued
Array ( [id] => 19500134 [patent_doc_number] => 20240339152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Data Sense Amplifier Circuit with a Hybrid Architecture [patent_app_type] => utility [patent_app_number] => 18/627960 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/627960
Data sense amplifier circuit with a hybrid architecture Apr 4, 2024 Issued
Array ( [id] => 19335362 [patent_doc_number] => 20240249792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SYSTEM AND METHOD FOR EXTENDING LIFETIME OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/625895 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625895
SYSTEM AND METHOD FOR EXTENDING LIFETIME OF MEMORY DEVICE Apr 2, 2024 Pending
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