Search

Jay W. Radke

Examiner (ID: 3459, Phone: (571)270-1622 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1157
Issued Applications
986
Pending Applications
68
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17582620 [patent_doc_number] => 20220139475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE DEVICE, AND METHOD OF OPERATING THE DEVICE [patent_app_type] => utility [patent_app_number] => 17/328487 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328487
Non-volatile memory device, memory system including the device, and method of operating the device May 23, 2021 Issued
Array ( [id] => 18205220 [patent_doc_number] => 11587622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Non-volatile memory device including high voltage switching circuit, and operation method of the non-volatile memory device [patent_app_type] => utility [patent_app_number] => 17/326397 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326397
Non-volatile memory device including high voltage switching circuit, and operation method of the non-volatile memory device May 20, 2021 Issued
Array ( [id] => 17346823 [patent_doc_number] => 20220013154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => Low Power Content Addressable Memory [patent_app_type] => utility [patent_app_number] => 17/327602 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17327602 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/327602
Low Power Content Addressable Memory May 20, 2021 Abandoned
Array ( [id] => 18721281 [patent_doc_number] => 11798633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Methods and apparatuses including an asymmetric assist device [patent_app_type] => utility [patent_app_number] => 17/327238 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6227 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17327238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/327238
Methods and apparatuses including an asymmetric assist device May 20, 2021 Issued
Array ( [id] => 20111267 [patent_doc_number] => 12362002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Staggered read recovery for improved read window budget in a three dimensional (3D) NAND memory array [patent_app_type] => utility [patent_app_number] => 17/322724 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5878 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322724
Staggered read recovery for improved read window budget in a three dimensional (3D) NAND memory array May 16, 2021 Issued
Array ( [id] => 17941502 [patent_doc_number] => 11475961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Nonvolatile memory with efficient look-ahead read [patent_app_type] => utility [patent_app_number] => 17/307396 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 12569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/307396
Nonvolatile memory with efficient look-ahead read May 3, 2021 Issued
Array ( [id] => 17188521 [patent_doc_number] => 20210335406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => MECHANISM TO IMPROVE DRIVER CAPABILITY WITH FINE TUNED CALIBRATION RESISTOR [patent_app_type] => utility [patent_app_number] => 17/306893 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306893
Mechanism to improve driver capability with fine tuned calibration resistor May 2, 2021 Issued
Array ( [id] => 18593127 [patent_doc_number] => 11742036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Reducing maximum programming voltage in memory programming operations [patent_app_type] => utility [patent_app_number] => 17/306347 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9070 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306347
Reducing maximum programming voltage in memory programming operations May 2, 2021 Issued
Array ( [id] => 17941501 [patent_doc_number] => 11475960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Non-volatile memory device with a program driver circuit including a voltage limiter [patent_app_type] => utility [patent_app_number] => 17/306266 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306266
Non-volatile memory device with a program driver circuit including a voltage limiter May 2, 2021 Issued
Array ( [id] => 18000729 [patent_doc_number] => 11501840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Proximity disturb remediation based on a number of programmed memory cells [patent_app_type] => utility [patent_app_number] => 17/243386 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/243386
Proximity disturb remediation based on a number of programmed memory cells Apr 27, 2021 Issued
Array ( [id] => 19765694 [patent_doc_number] => 12223992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => High-density low voltage ferroelectric differential memory bit-cell with shared plate- line [patent_app_type] => utility [patent_app_number] => 17/243451 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13009 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/243451
High-density low voltage ferroelectric differential memory bit-cell with shared plate- line Apr 27, 2021 Issued
Array ( [id] => 17025212 [patent_doc_number] => 20210249084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => HIGH-VOLTAGE SHIFTER WITH REDUCED TRANSISTOR DEGRADATION [patent_app_type] => utility [patent_app_number] => 17/240358 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240358
High-voltage shifter with reduced transistor degradation Apr 25, 2021 Issued
Array ( [id] => 18088398 [patent_doc_number] => 11538537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Negative gate stress operation in multi-pass programming and memory device thereof [patent_app_type] => utility [patent_app_number] => 17/232059 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 16740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232059
Negative gate stress operation in multi-pass programming and memory device thereof Apr 14, 2021 Issued
Array ( [id] => 17847724 [patent_doc_number] => 11437108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-06 [patent_title] => Voltage bin calibration based on a temporary voltage shift offset [patent_app_type] => utility [patent_app_number] => 17/230786 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 16449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230786 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/230786
Voltage bin calibration based on a temporary voltage shift offset Apr 13, 2021 Issued
Array ( [id] => 16995169 [patent_doc_number] => 20210233589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/227820 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/227820
Concurrent programming of multiple cells for non-volatile memory devices Apr 11, 2021 Issued
Array ( [id] => 17878365 [patent_doc_number] => 11450386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Nonvolatile memory device performing two-way channel precharge [patent_app_type] => utility [patent_app_number] => 17/221833 [patent_app_country] => US [patent_app_date] => 2021-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 16356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221833 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/221833
Nonvolatile memory device performing two-way channel precharge Apr 3, 2021 Issued
Array ( [id] => 17878344 [patent_doc_number] => 11450365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Input/output circuit, operation method of the input/output circuit and data processing system including the input/output circuit [patent_app_type] => utility [patent_app_number] => 17/221312 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5810 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/221312
Input/output circuit, operation method of the input/output circuit and data processing system including the input/output circuit Apr 1, 2021 Issued
Array ( [id] => 17787600 [patent_doc_number] => 11410734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-09 [patent_title] => Voltage bin selection for blocks of a memory device after power up of the memory device [patent_app_type] => utility [patent_app_number] => 17/219498 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219498 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219498
Voltage bin selection for blocks of a memory device after power up of the memory device Mar 30, 2021 Issued
Array ( [id] => 17708266 [patent_doc_number] => 20220208274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY DEVICE INCLUDING VOLTAGE CONTROL FOR DIFUSSION REGIONS ASSOCIATED WITH MEMORY BLOCKS [patent_app_type] => utility [patent_app_number] => 17/217014 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217014
Memory device including voltage control for diffusion regions associated with memory blocks Mar 29, 2021 Issued
Array ( [id] => 17558893 [patent_doc_number] => 11315612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Semiconductor storing apparatus and pre-charge method [patent_app_type] => utility [patent_app_number] => 17/216713 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216713
Semiconductor storing apparatus and pre-charge method Mar 29, 2021 Issued
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