Search

Jay W. Radke

Examiner (ID: 9961, Phone: (571)270-1622 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1108
Issued Applications
954
Pending Applications
63
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19335362 [patent_doc_number] => 20240249792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SYSTEM AND METHOD FOR EXTENDING LIFETIME OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/625895 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625895
SYSTEM AND METHOD FOR EXTENDING LIFETIME OF MEMORY DEVICE Apr 2, 2024 Pending
Array ( [id] => 20250870 [patent_doc_number] => 20250299739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => NONVOLATILE MEMORY WITH FAST PROGRAM VOLTAGE RAMP DOWN [patent_app_type] => utility [patent_app_number] => 18/614774 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614774
NONVOLATILE MEMORY WITH FAST PROGRAM VOLTAGE RAMP DOWN Mar 24, 2024 Pending
Array ( [id] => 20250870 [patent_doc_number] => 20250299739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => NONVOLATILE MEMORY WITH FAST PROGRAM VOLTAGE RAMP DOWN [patent_app_type] => utility [patent_app_number] => 18/614774 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614774
NONVOLATILE MEMORY WITH FAST PROGRAM VOLTAGE RAMP DOWN Mar 24, 2024 Pending
Array ( [id] => 20250869 [patent_doc_number] => 20250299738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => SYSTEM AND METHOD FOR IMPROVED ENDURANCE IN NON-VOLATILE MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/612211 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612211 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612211
SYSTEM AND METHOD FOR IMPROVED ENDURANCE IN NON-VOLATILE MEMORY SYSTEMS Mar 20, 2024 Pending
Array ( [id] => 19531488 [patent_doc_number] => 20240355390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => STORAGE SYSTEM FOR PROCESSING GENOME SEQUENCES [patent_app_type] => utility [patent_app_number] => 18/595672 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595672
STORAGE SYSTEM FOR PROCESSING GENOME SEQUENCES Mar 4, 2024 Pending
Array ( [id] => 19531488 [patent_doc_number] => 20240355390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => STORAGE SYSTEM FOR PROCESSING GENOME SEQUENCES [patent_app_type] => utility [patent_app_number] => 18/595672 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595672
STORAGE SYSTEM FOR PROCESSING GENOME SEQUENCES Mar 4, 2024 Pending
Array ( [id] => 19893050 [patent_doc_number] => 20250118362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE COMPLEX [patent_app_type] => utility [patent_app_number] => 18/581069 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581069
BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE COMPLEX Feb 18, 2024 Pending
Array ( [id] => 19893050 [patent_doc_number] => 20250118362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE COMPLEX [patent_app_type] => utility [patent_app_number] => 18/581069 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581069
BANKED SENSE AMPLIFIER CIRCUIT FOR A MEMORY CORE AND A MEMORY CORE COMPLEX Feb 18, 2024 Pending
Array ( [id] => 20375087 [patent_doc_number] => 12482529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory with built-in synchronous-write-through redundancy and associated test method [patent_app_type] => utility [patent_app_number] => 18/443347 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443347
Memory with built-in synchronous-write-through redundancy and associated test method Feb 15, 2024 Issued
Array ( [id] => 20375087 [patent_doc_number] => 12482529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory with built-in synchronous-write-through redundancy and associated test method [patent_app_type] => utility [patent_app_number] => 18/443347 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443347 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443347
Memory with built-in synchronous-write-through redundancy and associated test method Feb 15, 2024 Issued
Array ( [id] => 19985738 [patent_doc_number] => 20250123960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM, COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/442027 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442027 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442027
MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM, COMPUTER-READABLE STORAGE MEDIUM Feb 13, 2024 Pending
Array ( [id] => 19192255 [patent_doc_number] => 20240171168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => DELAY CALIBRATION CIRCUIT, MEMORY, AND CLOCK SIGNAL CALIBRATION METHOD [patent_app_type] => utility [patent_app_number] => 18/428328 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428328 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428328
DELAY CALIBRATION CIRCUIT, MEMORY, AND CLOCK SIGNAL CALIBRATION METHOD Jan 30, 2024 Issued
Array ( [id] => 19348886 [patent_doc_number] => 20240257850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/426825 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426825 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426825
MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM Jan 29, 2024 Pending
Array ( [id] => 19335352 [patent_doc_number] => 20240249782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/423047 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423047
MEMORY SYSTEM AND OPERATING METHOD THEREOF Jan 24, 2024 Pending
Array ( [id] => 20028488 [patent_doc_number] => 20250166710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => OPERATION METHODS OF MEMORY, MEMORY AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/422919 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422919
OPERATION METHODS OF MEMORY, MEMORY AND MEMORY SYSTEMS Jan 24, 2024 Pending
Array ( [id] => 19712357 [patent_doc_number] => 20250022499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/403739 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403739
MEMORY SYSTEM AND OPERATING METHOD Jan 3, 2024 Pending
Array ( [id] => 19160856 [patent_doc_number] => 20240153563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND STORAGE SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/545144 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545144 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545144
Semiconductor memory device and storage system including semiconductor memory device Dec 18, 2023 Issued
Array ( [id] => 19788253 [patent_doc_number] => 20250061932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR PERFORMING PHASE ADJUSTMENT OPERATION [patent_app_type] => utility [patent_app_number] => 18/541678 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/541678
ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR PERFORMING PHASE ADJUSTMENT OPERATION Dec 14, 2023 Pending
Array ( [id] => 19788253 [patent_doc_number] => 20250061932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR PERFORMING PHASE ADJUSTMENT OPERATION [patent_app_type] => utility [patent_app_number] => 18/541678 [patent_app_country] => US [patent_app_date] => 2023-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18541678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/541678
ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR PERFORMING PHASE ADJUSTMENT OPERATION Dec 14, 2023 Pending
Array ( [id] => 19100784 [patent_doc_number] => 20240120012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => MULTI-SAMPLED, CHARGE-SHARING THERMOMETER IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/539798 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/539798
Multi-sampled, charge-sharing thermometer in memory device Dec 13, 2023 Issued
Menu