Search

Jay W. Radke

Examiner (ID: 4418, Phone: (571)270-1622 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1138
Issued Applications
969
Pending Applications
68
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15351151 [patent_doc_number] => 20200013467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATION [patent_app_type] => utility [patent_app_number] => 16/574669 [patent_app_country] => US [patent_app_date] => 2019-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/574669
Memory device and method of operation Sep 17, 2019 Issued
Array ( [id] => 16097923 [patent_doc_number] => 20200202948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/561454 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561454
Semiconductor memory device Sep 4, 2019 Issued
Array ( [id] => 17195874 [patent_doc_number] => 11164639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/561094 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 20448 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561094 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561094
Semiconductor memory device Sep 4, 2019 Issued
Array ( [id] => 15839977 [patent_doc_number] => 20200135271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/560472 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560472 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560472
Semiconductor memory device Sep 3, 2019 Issued
Array ( [id] => 16536263 [patent_doc_number] => 10878876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Apparatuses and methods for providing power for memory refresh operations [patent_app_type] => utility [patent_app_number] => 16/557948 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5195 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557948
Apparatuses and methods for providing power for memory refresh operations Aug 29, 2019 Issued
Array ( [id] => 16130103 [patent_doc_number] => 10698812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Updating cache using two bloom filters [patent_app_type] => utility [patent_app_number] => 16/550613 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6086 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550613 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550613
Updating cache using two bloom filters Aug 25, 2019 Issued
Array ( [id] => 15461469 [patent_doc_number] => 20200043559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => MANAGED NAND PERFORMANCE THROTTLING [patent_app_type] => utility [patent_app_number] => 16/542963 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542963
Managed NAND performance throttling Aug 15, 2019 Issued
Array ( [id] => 16684157 [patent_doc_number] => 10943646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Memory device, driving method thereof, semiconductor device, electronic component, and electronic device [patent_app_type] => utility [patent_app_number] => 16/541239 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 55 [patent_no_of_words] => 15844 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541239
Memory device, driving method thereof, semiconductor device, electronic component, and electronic device Aug 14, 2019 Issued
Array ( [id] => 15214371 [patent_doc_number] => 20190369872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => BANK TO BANK DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 16/541764 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541764
Bank to bank data transfer Aug 14, 2019 Issued
Array ( [id] => 15184335 [patent_doc_number] => 20190362759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => APPARATUSES AND METHODS TO SELECTIVELY PERFORM LOGICAL OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/537775 [patent_app_country] => US [patent_app_date] => 2019-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537775 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537775
Apparatuses and methods to selectively perform logical operations Aug 11, 2019 Issued
Array ( [id] => 16339050 [patent_doc_number] => 10790017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Nonvolatile memory and writing method [patent_app_type] => utility [patent_app_number] => 16/529322 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 57 [patent_no_of_words] => 19452 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 735 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529322
Nonvolatile memory and writing method Jul 31, 2019 Issued
Array ( [id] => 15153837 [patent_doc_number] => 20190355396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => CONTROL METHOD FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/526589 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526589 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526589
CONTROL METHOD FOR MEMORY DEVICE Jul 29, 2019 Abandoned
Array ( [id] => 16356239 [patent_doc_number] => 10796756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Permutation coding for improved memory cell operations [patent_app_type] => utility [patent_app_number] => 16/524288 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6314 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16524288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/524288
Permutation coding for improved memory cell operations Jul 28, 2019 Issued
Array ( [id] => 15153841 [patent_doc_number] => 20190355398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => MEMORY DEVICE WITH SHARED AMPLIFIER CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/518146 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518146
Memory device with shared amplifier circuitry Jul 21, 2019 Issued
Array ( [id] => 16347767 [patent_doc_number] => 20200312418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING IN NON-VOLATILE MEMORY DEVICE BY APPLYING MULTIPLE BITLINE BIAS VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/516226 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516226 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516226
Non-volatile memory device and method for programming in non-volatile memory device by applying multiple bitline bias voltages Jul 17, 2019 Issued
Array ( [id] => 16536317 [patent_doc_number] => 10878930 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Layout structure of memory array [patent_app_type] => utility [patent_app_number] => 16/509524 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/509524
Layout structure of memory array Jul 11, 2019 Issued
Array ( [id] => 16097907 [patent_doc_number] => 20200202940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/509864 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509864 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/509864
Semiconductor device and a manufacturing method of the semiconductor device Jul 11, 2019 Issued
Array ( [id] => 15442179 [patent_doc_number] => 20200035273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND READ METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/509954 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/509954
Semiconductor storage device and read method thereof Jul 11, 2019 Issued
Array ( [id] => 17326266 [patent_doc_number] => 11217291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Circuitry borrowing for memory arrays [patent_app_type] => utility [patent_app_number] => 16/508772 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 27635 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508772 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/508772
Circuitry borrowing for memory arrays Jul 10, 2019 Issued
Array ( [id] => 16578421 [patent_doc_number] => 20210012822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => SENSING SCHEME FOR STT-MRAM USING LOW-BARRIER NANOMAGNETS [patent_app_type] => utility [patent_app_number] => 16/508940 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508940 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/508940
Sensing scheme for STT-MRAM using low-barrier nanomagnets Jul 10, 2019 Issued
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