
Jay W. Radke
Examiner (ID: 3459, Phone: (571)270-1622 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 1157 |
| Issued Applications | 986 |
| Pending Applications | 68 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16904534
[patent_doc_number] => 20210183450
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-17
[patent_title] => ERASE SUSPEND SCHEME IN A STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/710526
[patent_app_country] => US
[patent_app_date] => 2019-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6559
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710526
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/710526 | Erase suspend scheme in a storage device | Dec 10, 2019 | Issued |
Array
(
[id] => 16147675
[patent_doc_number] => 10706912
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-07
[patent_title] => Memories configured to control discharge of a control gate voltage of a transistor connected between a data line and a common source
[patent_app_type] => utility
[patent_app_number] => 16/710006
[patent_app_country] => US
[patent_app_date] => 2019-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9106
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 288
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710006
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/710006 | Memories configured to control discharge of a control gate voltage of a transistor connected between a data line and a common source | Dec 10, 2019 | Issued |
Array
(
[id] => 16738729
[patent_doc_number] => 10964390
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-30
[patent_title] => Skip coding for fractional bit-per-cell NAND memories
[patent_app_type] => utility
[patent_app_number] => 16/709338
[patent_app_country] => US
[patent_app_date] => 2019-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 5280
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709338
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/709338 | Skip coding for fractional bit-per-cell NAND memories | Dec 9, 2019 | Issued |
Array
(
[id] => 16752267
[patent_doc_number] => 20210104279
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => SINGLE-GATE MULTIPLE-TIME PROGRAMMING NON-VOLATILE MEMORY ARRAY AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/708888
[patent_app_country] => US
[patent_app_date] => 2019-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3574
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16708888
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/708888 | SINGLE-GATE MULTIPLE-TIME PROGRAMMING NON-VOLATILE MEMORY ARRAY AND OPERATING METHOD THEREOF | Dec 9, 2019 | Abandoned |
Array
(
[id] => 16942985
[patent_doc_number] => 11055227
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-06
[patent_title] => Controller and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 16/702795
[patent_app_country] => US
[patent_app_date] => 2019-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 18
[patent_no_of_words] => 9443
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702795
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/702795 | Controller and operating method thereof | Dec 3, 2019 | Issued |
Array
(
[id] => 16192921
[patent_doc_number] => 20200233770
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-23
[patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/696396
[patent_app_country] => US
[patent_app_date] => 2019-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14259
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696396
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/696396 | Memory system and operating method thereof | Nov 25, 2019 | Issued |
Array
(
[id] => 16928062
[patent_doc_number] => 11049551
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-29
[patent_title] => Memory devices providing in situ computing using sequential transfer of row buffered data and related methods and circuits
[patent_app_type] => utility
[patent_app_number] => 16/682151
[patent_app_country] => US
[patent_app_date] => 2019-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7713
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682151
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/682151 | Memory devices providing in situ computing using sequential transfer of row buffered data and related methods and circuits | Nov 12, 2019 | Issued |
Array
(
[id] => 16810994
[patent_doc_number] => 20210133549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => CHARGE-SHARING COMPUTE-IN-MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/669855
[patent_app_country] => US
[patent_app_date] => 2019-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669855
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/669855 | Charge-sharing compute-in-memory system | Oct 30, 2019 | Issued |
Array
(
[id] => 16119187
[patent_doc_number] => 20200211616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/661342
[patent_app_country] => US
[patent_app_date] => 2019-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6193
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661342
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/661342 | Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus | Oct 22, 2019 | Issued |
Array
(
[id] => 16179105
[patent_doc_number] => 20200226073
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => RANDOM CODE GENERATOR WITH NON-VOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 16/661012
[patent_app_country] => US
[patent_app_date] => 2019-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4890
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661012
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/661012 | Random code generator with non-volatile memory | Oct 22, 2019 | Issued |
Array
(
[id] => 16699683
[patent_doc_number] => 10950291
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-16
[patent_title] => Apparatuses and methods to perform duty cycle adjustment with back-bias voltage
[patent_app_type] => utility
[patent_app_number] => 16/661784
[patent_app_country] => US
[patent_app_date] => 2019-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9157
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661784
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/661784 | Apparatuses and methods to perform duty cycle adjustment with back-bias voltage | Oct 22, 2019 | Issued |
Array
(
[id] => 17018193
[patent_doc_number] => 11087838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-10
[patent_title] => Voltage drivers with reduced power consumption during polarity transition
[patent_app_type] => utility
[patent_app_number] => 16/660594
[patent_app_country] => US
[patent_app_date] => 2019-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4215
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660594
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/660594 | Voltage drivers with reduced power consumption during polarity transition | Oct 21, 2019 | Issued |
Array
(
[id] => 17062901
[patent_doc_number] => 11107510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-31
[patent_title] => Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions
[patent_app_type] => utility
[patent_app_number] => 16/657445
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10779
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657445
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/657445 | Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions | Oct 17, 2019 | Issued |
Array
(
[id] => 15459225
[patent_doc_number] => 20200042437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-06
[patent_title] => METHOD FOR MANAGING A MEMORY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/596703
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14562
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596703
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/596703 | Method for managing a memory apparatus | Oct 7, 2019 | Issued |
Array
(
[id] => 15775209
[patent_doc_number] => 20200118622
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => LINEARLY WEIGHT UPDATABLE CMOS SYNAPTIC ARRAY WITHOUT CELL LOCATION DEPENDENCE
[patent_app_type] => utility
[patent_app_number] => 16/592334
[patent_app_country] => US
[patent_app_date] => 2019-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7054
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592334
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/592334 | Linearly weight updatable CMOS synaptic array without cell location dependence | Oct 2, 2019 | Issued |
Array
(
[id] => 16684158
[patent_doc_number] => 10943647
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-09
[patent_title] => Bit-line mux driver with diode header for computer memory
[patent_app_type] => utility
[patent_app_number] => 16/587560
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6153
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587560
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/587560 | Bit-line mux driver with diode header for computer memory | Sep 29, 2019 | Issued |
Array
(
[id] => 16865619
[patent_doc_number] => 11024370
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Static random access memory with write assist adjustment
[patent_app_type] => utility
[patent_app_number] => 16/587504
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8994
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587504
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/587504 | Static random access memory with write assist adjustment | Sep 29, 2019 | Issued |
Array
(
[id] => 16653148
[patent_doc_number] => 10930339
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-02-23
[patent_title] => Voltage bitline high (VBLH) regulation for computer memory
[patent_app_type] => utility
[patent_app_number] => 16/587496
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5892
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587496
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/587496 | Voltage bitline high (VBLH) regulation for computer memory | Sep 29, 2019 | Issued |
Array
(
[id] => 16447975
[patent_doc_number] => 10839906
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-17
[patent_title] => In memory computing (IMC) memory circuit having 6T cells
[patent_app_type] => utility
[patent_app_number] => 16/588140
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 15021
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588140
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/588140 | In memory computing (IMC) memory circuit having 6T cells | Sep 29, 2019 | Issued |
Array
(
[id] => 15351151
[patent_doc_number] => 20200013467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-09
[patent_title] => MEMORY DEVICE AND METHOD OF OPERATION
[patent_app_type] => utility
[patent_app_number] => 16/574669
[patent_app_country] => US
[patent_app_date] => 2019-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15582
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574669
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/574669 | Memory device and method of operation | Sep 17, 2019 | Issued |