
Jay W. Radke
Examiner (ID: 3459, Phone: (571)270-1622 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 1157 |
| Issued Applications | 986 |
| Pending Applications | 68 |
| Abandoned Applications | 129 |
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|---|---|---|---|
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