Search

Jay W. Radke

Examiner (ID: 9961, Phone: (571)270-1622 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1108
Issued Applications
954
Pending Applications
63
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20132074 [patent_doc_number] => 12374391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Static random access memory with write assist adjustment [patent_app_type] => utility [patent_app_number] => 18/182956 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182956 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182956
Static random access memory with write assist adjustment Mar 12, 2023 Issued
Array ( [id] => 20132074 [patent_doc_number] => 12374391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Static random access memory with write assist adjustment [patent_app_type] => utility [patent_app_number] => 18/182956 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182956 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182956
Static random access memory with write assist adjustment Mar 12, 2023 Issued
Array ( [id] => 18696102 [patent_doc_number] => 20230326533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => MEMORY DEVICE CAPABLE OF OPERATING MULTIPLE PLANES SIMULTANEOUSLY [patent_app_type] => utility [patent_app_number] => 18/181577 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181577 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/181577
MEMORY DEVICE CAPABLE OF OPERATING MULTIPLE PLANES SIMULTANEOUSLY Mar 9, 2023 Pending
Array ( [id] => 19007361 [patent_doc_number] => 20240071432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY DEVICE OF REDUCING THE NUMBER OF CALIBRATION RESISTORS AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/116823 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18116823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/116823
Memory device of reducing the number of calibration resistors and control method thereof Mar 1, 2023 Issued
Array ( [id] => 18661034 [patent_doc_number] => 20230307047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => REDUCING PRECHARGE CURRENT SURGE IN DIGITAL COMPUTE IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/175514 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175514 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175514
Reducing precharge current surge in digital compute in memory Feb 26, 2023 Issued
Array ( [id] => 18472737 [patent_doc_number] => 20230207025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/173499 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/173499
Semiconductor device and memory system Feb 22, 2023 Issued
Array ( [id] => 19392516 [patent_doc_number] => 20240282386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/172308 [patent_app_country] => US [patent_app_date] => 2023-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/172308
MEMORY DEVICE Feb 21, 2023 Abandoned
Array ( [id] => 19972223 [patent_doc_number] => 12340841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Multi-rail sense circuit with pre-charge transistors and memory circuit incorporating the sense circuit [patent_app_type] => utility [patent_app_number] => 18/170925 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2465 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170925 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170925
Multi-rail sense circuit with pre-charge transistors and memory circuit incorporating the sense circuit Feb 16, 2023 Issued
Array ( [id] => 19016064 [patent_doc_number] => 11923004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Systems and methods for writing and reading data stored in a polymer [patent_app_type] => utility [patent_app_number] => 18/171106 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 20381 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171106
Systems and methods for writing and reading data stored in a polymer Feb 16, 2023 Issued
Array ( [id] => 20080565 [patent_doc_number] => 12354640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Memory device refresh operations [patent_app_type] => utility [patent_app_number] => 18/171121 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171121 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171121
Memory device refresh operations Feb 16, 2023 Issued
Array ( [id] => 19054470 [patent_doc_number] => 20240096439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SELECTIVE PER DIE DRAM PPR FOR CXL TYPE 3 DEVICE [patent_app_type] => utility [patent_app_number] => 18/169635 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169635
Selective per die DRAM PPR for memory device Feb 14, 2023 Issued
Array ( [id] => 20161157 [patent_doc_number] => 12387790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Double single level cell program in a memory device [patent_app_type] => utility [patent_app_number] => 18/104201 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4530 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104201
Double single level cell program in a memory device Jan 30, 2023 Issued
Array ( [id] => 18423688 [patent_doc_number] => 20230178152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/161274 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161274 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/161274
Semiconductor storage device Jan 29, 2023 Issued
Array ( [id] => 18408677 [patent_doc_number] => 20230170030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/160620 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160620 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160620
Nonvolatile memory device and storage device including the nonvolatile memory device Jan 26, 2023 Issued
Array ( [id] => 18394550 [patent_doc_number] => 20230162771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => ACTIVATE COMMANDS FOR MEMORY PREPARATION [patent_app_type] => utility [patent_app_number] => 18/100806 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100806
Activate commands for memory preparation Jan 23, 2023 Issued
Array ( [id] => 18983330 [patent_doc_number] => 11908515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => 2T-1R architecture for resistive ram [patent_app_type] => utility [patent_app_number] => 18/098548 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 64 [patent_no_of_words] => 13055 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18098548 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/098548
2T-1R architecture for resistive ram Jan 17, 2023 Issued
Array ( [id] => 18615527 [patent_doc_number] => 20230282264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => Memory Arrays, Methods of Forming the Same, and Methods of Operating the Same [patent_app_type] => utility [patent_app_number] => 18/154244 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154244
Memory Arrays, Methods of Forming the Same, and Methods of Operating the Same Jan 12, 2023 Pending
Array ( [id] => 18615527 [patent_doc_number] => 20230282264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => Memory Arrays, Methods of Forming the Same, and Methods of Operating the Same [patent_app_type] => utility [patent_app_number] => 18/154244 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154244
Memory Arrays, Methods of Forming the Same, and Methods of Operating the Same Jan 12, 2023 Pending
Array ( [id] => 18347305 [patent_doc_number] => 20230135415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => ARCHITECTURE AND METHOD FOR NAND MEMORY OPERATION [patent_app_type] => utility [patent_app_number] => 18/091131 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091131 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091131
ARCHITECTURE AND METHOD FOR NAND MEMORY OPERATION Dec 28, 2022 Pending
Array ( [id] => 18934109 [patent_doc_number] => 11886538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Histogram creation process for memory devices [patent_app_type] => utility [patent_app_number] => 18/091002 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091002
Histogram creation process for memory devices Dec 28, 2022 Issued
Menu