Search

Jay W. Radke

Examiner (ID: 9961, Phone: (571)270-1622 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1108
Issued Applications
954
Pending Applications
63
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19007435 [patent_doc_number] => 20240071506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => PARTIAL BLOCK READ VOLTAGE OFFSET [patent_app_type] => utility [patent_app_number] => 17/823191 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823191
PARTIAL BLOCK READ VOLTAGE OFFSET Aug 29, 2022 Pending
Array ( [id] => 18631520 [patent_doc_number] => 20230290422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => CIRCUIT AND METHOD FOR TESTING MEMORY CHIP [patent_app_type] => utility [patent_app_number] => 17/898516 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898516
CIRCUIT AND METHOD FOR TESTING MEMORY CHIP Aug 29, 2022 Abandoned
Array ( [id] => 19376477 [patent_doc_number] => 12068055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Managing performance and service life prediction for a memory subsystem using environmental factors [patent_app_type] => utility [patent_app_number] => 17/899417 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899417 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899417
Managing performance and service life prediction for a memory subsystem using environmental factors Aug 29, 2022 Issued
Array ( [id] => 19007435 [patent_doc_number] => 20240071506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => PARTIAL BLOCK READ VOLTAGE OFFSET [patent_app_type] => utility [patent_app_number] => 17/823191 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13837 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823191
PARTIAL BLOCK READ VOLTAGE OFFSET Aug 29, 2022 Pending
Array ( [id] => 19007457 [patent_doc_number] => 20240071528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/897441 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897441
Managing defective blocks during multi-plane programming operations in memory devices Aug 28, 2022 Issued
Array ( [id] => 19552758 [patent_doc_number] => 12136469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/896907 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16019 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896907
Semiconductor memory device Aug 25, 2022 Issued
Array ( [id] => 19007386 [patent_doc_number] => 20240071457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => Digit Line Voltage Boosting Systems and Methods [patent_app_type] => utility [patent_app_number] => 17/896345 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896345
Digit line voltage boosting systems and methods Aug 25, 2022 Issued
Array ( [id] => 18585714 [patent_doc_number] => 20230267978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/895956 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895956
Semiconductor device and memory system Aug 24, 2022 Issued
Array ( [id] => 18229017 [patent_doc_number] => 20230068011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SYSTEM AND METHOD FOR READING AND WRITING MEMORY MANAGEMENT DATA THROUGH A NON-VOLATILE CELL BASED REGISTER [patent_app_type] => utility [patent_app_number] => 17/895565 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895565
System and method for reading and writing memory management data through a non-volatile cell based register Aug 24, 2022 Issued
Array ( [id] => 19459965 [patent_doc_number] => 12100467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Systems and methods for testing redundant fuse latches in a memory device [patent_app_type] => utility [patent_app_number] => 17/822032 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5252 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822032
Systems and methods for testing redundant fuse latches in a memory device Aug 23, 2022 Issued
Array ( [id] => 19328633 [patent_doc_number] => 12046322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Configurable data protection circuitry for memory devices [patent_app_type] => utility [patent_app_number] => 17/895053 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895053
Configurable data protection circuitry for memory devices Aug 23, 2022 Issued
Array ( [id] => 18990863 [patent_doc_number] => 20240062832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => 3D NAND MEMORY WITH FAST CORRECTIVE READ [patent_app_type] => utility [patent_app_number] => 17/891544 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891544
3D NAND memory with fast corrective read Aug 18, 2022 Issued
Array ( [id] => 18781983 [patent_doc_number] => 11823748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Voltage bin calibration based on a temporary voltage shift offset [patent_app_type] => utility [patent_app_number] => 17/820792 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 16478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/820792
Voltage bin calibration based on a temporary voltage shift offset Aug 17, 2022 Issued
Array ( [id] => 18431437 [patent_doc_number] => 11676664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Voltage bin selection for blocks of a memory device after power up of the memory device [patent_app_type] => utility [patent_app_number] => 17/883538 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883538
Voltage bin selection for blocks of a memory device after power up of the memory device Aug 7, 2022 Issued
Array ( [id] => 18408673 [patent_doc_number] => 20230170026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => METHOD AND APPARATUS WITH MEMORY ARRAY PROGRAMING [patent_app_type] => utility [patent_app_number] => 17/880849 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880849
Method and apparatus with memory array programming Aug 3, 2022 Issued
Array ( [id] => 19356710 [patent_doc_number] => 12057165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Method of programming a select transistor of a semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/879975 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 34 [patent_no_of_words] => 12630 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879975
Method of programming a select transistor of a semiconductor memory device Aug 2, 2022 Issued
Array ( [id] => 18958670 [patent_doc_number] => 20240046997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => NON-VOLATILE MEMORY DEVICE FOR MITIGATING CYCLING TRAPPED EFFECT AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/878933 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878933
Non-volatile memory device for mitigating cycling trapped effect and control method thereof Aug 1, 2022 Issued
Array ( [id] => 19494110 [patent_doc_number] => 12112831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Memory row-hammer mitigation [patent_app_type] => utility [patent_app_number] => 17/877592 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15864 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877592
Memory row-hammer mitigation Jul 28, 2022 Issued
Array ( [id] => 18548051 [patent_doc_number] => 11721409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Smart sampling for block family scan [patent_app_type] => utility [patent_app_number] => 17/877810 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 22769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877810
Smart sampling for block family scan Jul 28, 2022 Issued
Array ( [id] => 18639272 [patent_doc_number] => 11763888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => Range segmenting for analog CAM with improved precision [patent_app_type] => utility [patent_app_number] => 17/872923 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872923
Range segmenting for analog CAM with improved precision Jul 24, 2022 Issued
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