Jay-ming Wang

Array ( [id] => 6629920 [patent_doc_number] => 20020086468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Crystallization method of amorphous silicon' [patent_app_type] => new [patent_app_number] => 09/998338 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3658 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20020086468.pdf [firstpage_image] =>[orig_patent_app_number] => 09998338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478208 [patent_doc_number] => 06451701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors' [patent_app_type] => B1 [patent_app_number] => 09/993068 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451701.pdf [firstpage_image] =>[orig_patent_app_number] => 09993068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1595596 [patent_doc_number] => 06492245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method of forming air gap isolation between a bit line contact structure and a capacitor under bit line structure' [patent_app_type] => B1 [patent_app_number] => 09/978228 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2917 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492245.pdf [firstpage_image] =>[orig_patent_app_number] => 09978228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6474455 [patent_doc_number] => 20020022356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Compatible IC packages and methods for ensuring migration path' [patent_app_type] => new [patent_app_number] => 09/925288 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4727 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20020022356.pdf [firstpage_image] =>[orig_patent_app_number] => 09925288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6986913 [patent_doc_number] => 20010036745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method of forming a mask' [patent_app_type] => new [patent_app_number] => 09/887214 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3358 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036745.pdf [firstpage_image] =>[orig_patent_app_number] => 09887214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1594390 [patent_doc_number] => 06383875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of forming a transistor gate' [patent_app_type] => B1 [patent_app_number] => 09/852449 [patent_app_country] => US [patent_app_date] => 2001-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4372 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383875.pdf [firstpage_image] =>[orig_patent_app_number] => 09852449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1574785 [patent_doc_number] => 06468901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Nickel silicide including iridium for use in ultra-shallow junctions with high thermal stability and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/847873 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3778 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468901.pdf [firstpage_image] =>[orig_patent_app_number] => 09847873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1574585 [patent_doc_number] => 06468840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Active matrix substrate and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/841074 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 207 [patent_no_of_words] => 14464 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468840.pdf [firstpage_image] =>[orig_patent_app_number] => 09841074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1532440 [patent_doc_number] => 06410385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'ROM-embedded-DRAM' [patent_app_type] => B1 [patent_app_number] => 09/833706 [patent_app_country] => US [patent_app_date] => 2001-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 4425 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410385.pdf [firstpage_image] =>[orig_patent_app_number] => 09833706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6908182 [patent_doc_number] => 20010010949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'Plastic molded type semiconductor device and fabrication process thereof' [patent_app_type] => new [patent_app_number] => 09/832008 [patent_app_country] => US [patent_app_date] => 2001-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7927 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010949.pdf [firstpage_image] =>[orig_patent_app_number] => 09832008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6896222 [patent_doc_number] => 20010027012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method for fabricating a contact layer' [patent_app_type] => new [patent_app_number] => 09/811798 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2744 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027012.pdf [firstpage_image] =>[orig_patent_app_number] => 09811798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7640329 [patent_doc_number] => 06395585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method for housing sensors in a package' [patent_app_type] => B2 [patent_app_number] => 09/804148 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1324 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395585.pdf [firstpage_image] =>[orig_patent_app_number] => 09804148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6884937 [patent_doc_number] => 20010039099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Method of forming STI oxide regions and alignment marks in a semiconductor structure with one masking step' [patent_app_type] => new [patent_app_number] => 09/779388 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4084 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039099.pdf [firstpage_image] =>[orig_patent_app_number] => 09779388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1561155 [patent_doc_number] => 06362073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method for forming semiconductor device having low parasite capacitance using air gap and self-aligned contact plug' [patent_app_type] => B1 [patent_app_number] => 09/740948 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1889 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362073.pdf [firstpage_image] =>[orig_patent_app_number] => 09740948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6875596 [patent_doc_number] => 20010000689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new-utility [patent_app_number] => 09/736238 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9586 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000689.pdf [firstpage_image] =>[orig_patent_app_number] => 09736238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6902017 [patent_doc_number] => 20010000926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-10 [patent_title] => 'Method and materials for through-mask electroplating and selective base removal' [patent_app_type] => new-utility [patent_app_number] => 09/733188 [patent_app_country] => US [patent_app_date] => 2000-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3387 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000926.pdf [firstpage_image] =>[orig_patent_app_number] => 09733188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1446557 [patent_doc_number] => 06368912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of fabricating an isolation structure between a vertical transistor and a deep trench capacitor' [patent_app_type] => B1 [patent_app_number] => 09/733888 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3256 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368912.pdf [firstpage_image] =>[orig_patent_app_number] => 09733888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602604 [patent_doc_number] => 06432783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method for doping a semiconductor device through a mask' [patent_app_type] => B1 [patent_app_number] => 09/722818 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2986 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432783.pdf [firstpage_image] =>[orig_patent_app_number] => 09722818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7636601 [patent_doc_number] => 06380054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Schottky diode with reduced size' [patent_app_type] => B1 [patent_app_number] => 09/717591 [patent_app_country] => US [patent_app_date] => 2000-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 3973 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380054.pdf [firstpage_image] =>[orig_patent_app_number] => 09717591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1532416 [patent_doc_number] => 06410377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method for integrating CMOS sensor and high voltage device' [patent_app_type] => B1 [patent_app_number] => 09/707128 [patent_app_country] => US [patent_app_date] => 2000-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2194 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410377.pdf [firstpage_image] =>[orig_patent_app_number] => 09707128 [rel_patent_id] =>[rel_patent_doc_number] =>)