Jean C. Witz

Array ( [id] => 19865986 [patent_doc_number] => 20250104772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => MEMORY CELL VOLTAGE LEVEL SELECTION [patent_app_type] => utility [patent_app_number] => 18/971520 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20096085 [patent_doc_number] => 20250226021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => EDRAM CELL AND COMPUTE-IN-MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/963479 [patent_app_country] => US [patent_app_date] => 2024-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18963479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19851705 [patent_doc_number] => 20250097056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => NOVEL PUF GENERATORS BASED ON SRAM BIT CELLS [patent_app_type] => utility [patent_app_number] => 18/961173 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18961173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20071855 [patent_doc_number] => 20250210077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => DECISION FEEDBACK EQUALIZER, AND MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/955883 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20182109 [patent_doc_number] => 20250266067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => MEMORY CONTROLLER COMMUNICATING WITH VERTICALLY STACKED DIES AND SEMICONDUCTOR DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/955618 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19820671 [patent_doc_number] => 20250078878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/952783 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20088580 [patent_doc_number] => 20250218516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/952707 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19803728 [patent_doc_number] => 20250069653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => COMPUTING-IN-MEMORY CIRCUIT AND SRAM MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/947250 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19803726 [patent_doc_number] => 20250069651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => BISTABLE CIRCUIT AND ELECTRONIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/947451 [patent_app_country] => US [patent_app_date] => 2024-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18947451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19790114 [patent_doc_number] => 20250063793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ASSOCIATED MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/937075 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20250873 [patent_doc_number] => 20250299742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => DATA STORAGE DEVICE WHICH ERASES BY GROUPING MEMORY BLOCKS AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/935651 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20653946 [patent_doc_number] => 20260105970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => Read Operations in Memory Devices [patent_app_type] => utility [patent_app_number] => 18/932907 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19773095 [patent_doc_number] => 20250054521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/928444 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19757791 [patent_doc_number] => 20250046356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MEMORY AND ACCESS METHOD [patent_app_type] => utility [patent_app_number] => 18/921132 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18921132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20653952 [patent_doc_number] => 20260105976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => MERGING BLOCK FAMILIES IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/914480 [patent_app_country] => US [patent_app_date] => 2024-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18914480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20044603 [patent_doc_number] => 20250182825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => CONTENT ADDRESSABLE MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/893127 [patent_app_country] => US [patent_app_date] => 2024-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18893127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20071850 [patent_doc_number] => 20250210072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => BITLINE SENSING AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/883399 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19986774 [patent_doc_number] => 20250124996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/826151 [patent_app_country] => US [patent_app_date] => 2024-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20572059 [patent_doc_number] => 20260065987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => PROGRAMMING FOR NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/823332 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19820731 [patent_doc_number] => 20250078938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/823541 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823541 [rel_patent_id] =>[rel_patent_doc_number] =>)