Search

Jean F Duverne

Examiner (ID: 5108, Phone: (571)272-2091 , Office: P/2833 )

Most Active Art Unit
2833
Art Unit(s)
2833, 2839
Total Applications
3028
Issued Applications
2661
Pending Applications
105
Abandoned Applications
260

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3828293 [patent_doc_number] => 05739066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Semiconductor processing methods of forming a conductive gate and line' [patent_app_type] => 1 [patent_app_number] => 8/710353 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2525 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739066.pdf [firstpage_image] =>[orig_patent_app_number] => 710353 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710353
Semiconductor processing methods of forming a conductive gate and line Sep 16, 1996 Issued
Array ( [id] => 3885315 [patent_doc_number] => 05723370 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures' [patent_app_type] => 1 [patent_app_number] => 8/713061 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 57 [patent_no_of_words] => 5851 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/723/05723370.pdf [firstpage_image] =>[orig_patent_app_number] => 713061 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713061
FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures Sep 11, 1996 Issued
Array ( [id] => 3774035 [patent_doc_number] => 05817560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Ultra short trench transistors and process for making same' [patent_app_type] => 1 [patent_app_number] => 8/713281 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5974 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817560.pdf [firstpage_image] =>[orig_patent_app_number] => 713281 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713281
Ultra short trench transistors and process for making same Sep 11, 1996 Issued
Array ( [id] => 3791877 [patent_doc_number] => 05827411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Apparatus for electrolytic treatment of an electrolytic solution' [patent_app_type] => 1 [patent_app_number] => 8/716821 [patent_app_country] => US [patent_app_date] => 1996-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 10696 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/827/05827411.pdf [firstpage_image] =>[orig_patent_app_number] => 716821 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/716821
Apparatus for electrolytic treatment of an electrolytic solution Sep 9, 1996 Issued
Array ( [id] => 3725185 [patent_doc_number] => 05665243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method for removing metal contained in solution using surfactant having chelating ability' [patent_app_type] => 1 [patent_app_number] => 8/705674 [patent_app_country] => US [patent_app_date] => 1996-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4251 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665243.pdf [firstpage_image] =>[orig_patent_app_number] => 705674 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705674
Method for removing metal contained in solution using surfactant having chelating ability Aug 29, 1996 Issued
Array ( [id] => 3860900 [patent_doc_number] => 05795815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Integrated circuit scribe line structures and methods for making same' [patent_app_type] => 1 [patent_app_number] => 8/699492 [patent_app_country] => US [patent_app_date] => 1996-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 6403 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/795/05795815.pdf [firstpage_image] =>[orig_patent_app_number] => 699492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/699492
Integrated circuit scribe line structures and methods for making same Aug 18, 1996 Issued
Array ( [id] => 3860085 [patent_doc_number] => 05837119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Methods of fabricating dendritic powder materials for high conductivity paste applications' [patent_app_type] => 1 [patent_app_number] => 8/689553 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3170 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/837/05837119.pdf [firstpage_image] =>[orig_patent_app_number] => 689553 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/689553
Methods of fabricating dendritic powder materials for high conductivity paste applications Aug 8, 1996 Issued
Array ( [id] => 3762923 [patent_doc_number] => 05733420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Anodizing apparatus and an anodizing method' [patent_app_type] => 1 [patent_app_number] => 8/694210 [patent_app_country] => US [patent_app_date] => 1996-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 8501 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/733/05733420.pdf [firstpage_image] =>[orig_patent_app_number] => 694210 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/694210
Anodizing apparatus and an anodizing method Aug 7, 1996 Issued
Array ( [id] => 3877502 [patent_doc_number] => 05804497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Selectively doped channel region for increased I.sub.Dsat and method for making same' [patent_app_type] => 1 [patent_app_number] => 8/695101 [patent_app_country] => US [patent_app_date] => 1996-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 7130 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804497.pdf [firstpage_image] =>[orig_patent_app_number] => 695101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/695101
Selectively doped channel region for increased I.sub.Dsat and method for making same Aug 6, 1996 Issued
Array ( [id] => 3828033 [patent_doc_number] => 05739047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Method of fabricating a voidless IC electrical plug' [patent_app_type] => 1 [patent_app_number] => 8/691313 [patent_app_country] => US [patent_app_date] => 1996-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 1846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739047.pdf [firstpage_image] =>[orig_patent_app_number] => 691313 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691313
Method of fabricating a voidless IC electrical plug Aug 1, 1996 Issued
Array ( [id] => 3697025 [patent_doc_number] => 05677217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method for fabricating a mosfet device, with local channel doping and a titanium silicide gate' [patent_app_type] => 1 [patent_app_number] => 8/691287 [patent_app_country] => US [patent_app_date] => 1996-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2682 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677217.pdf [firstpage_image] =>[orig_patent_app_number] => 691287 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691287
Method for fabricating a mosfet device, with local channel doping and a titanium silicide gate Jul 31, 1996 Issued
Array ( [id] => 3786040 [patent_doc_number] => 05736445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method for producing at least two transsistors in a semiconductor body' [patent_app_type] => 1 [patent_app_number] => 8/683301 [patent_app_country] => US [patent_app_date] => 1996-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3679 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736445.pdf [firstpage_image] =>[orig_patent_app_number] => 683301 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/683301
Method for producing at least two transsistors in a semiconductor body Jul 17, 1996 Issued
Array ( [id] => 3730135 [patent_doc_number] => 05693563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Etch stop for copper damascene process' [patent_app_type] => 1 [patent_app_number] => 8/679973 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2378 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/693/05693563.pdf [firstpage_image] =>[orig_patent_app_number] => 679973 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679973
Etch stop for copper damascene process Jul 14, 1996 Issued
Array ( [id] => 3791631 [patent_doc_number] => 05726082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/670839 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1906 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726082.pdf [firstpage_image] =>[orig_patent_app_number] => 670839 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/670839
Semiconductor device and method for fabricating the same Jun 27, 1996 Issued
Array ( [id] => 3725163 [patent_doc_number] => 05700700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Transistor in a semiconductor device and method of making the same' [patent_app_type] => 1 [patent_app_number] => 8/665513 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1517 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/700/05700700.pdf [firstpage_image] =>[orig_patent_app_number] => 665513 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665513
Transistor in a semiconductor device and method of making the same Jun 17, 1996 Issued
Array ( [id] => 3681021 [patent_doc_number] => 05662788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Method for forming a metallization layer' [patent_app_type] => 1 [patent_app_number] => 8/656712 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1840 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/662/05662788.pdf [firstpage_image] =>[orig_patent_app_number] => 656712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656712
Method for forming a metallization layer Jun 2, 1996 Issued
Array ( [id] => 3651937 [patent_doc_number] => 05622611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Electroformed multilayer flow regulator incorporating force-generating means for selectively constricting the fluid flow path, and a process for the preparation thereof' [patent_app_type] => 1 [patent_app_number] => 8/653928 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 6548 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622611.pdf [firstpage_image] =>[orig_patent_app_number] => 653928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653928
Electroformed multilayer flow regulator incorporating force-generating means for selectively constricting the fluid flow path, and a process for the preparation thereof May 21, 1996 Issued
Array ( [id] => 3849601 [patent_doc_number] => 05767015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Metal plug with adhesion layer' [patent_app_type] => 1 [patent_app_number] => 8/651979 [patent_app_country] => US [patent_app_date] => 1996-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3441 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767015.pdf [firstpage_image] =>[orig_patent_app_number] => 651979 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651979
Metal plug with adhesion layer May 20, 1996 Issued
Array ( [id] => 3687654 [patent_doc_number] => 05679232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Process for making wire' [patent_app_type] => 1 [patent_app_number] => 8/634271 [patent_app_country] => US [patent_app_date] => 1996-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 20 [patent_no_of_words] => 6384 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/679/05679232.pdf [firstpage_image] =>[orig_patent_app_number] => 634271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634271
Process for making wire Apr 17, 1996 Issued
Array ( [id] => 3718688 [patent_doc_number] => 05672260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Process for selective application of solder to circuit packages' [patent_app_type] => 1 [patent_app_number] => 8/633322 [patent_app_country] => US [patent_app_date] => 1996-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6642 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/672/05672260.pdf [firstpage_image] =>[orig_patent_app_number] => 633322 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/633322
Process for selective application of solder to circuit packages Apr 16, 1996 Issued
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