![](/images/general/no_picture/200_user.png)
Jean F Duverne
Examiner (ID: 5108, Phone: (571)272-2091 , Office: P/2833 )
Most Active Art Unit | 2833 |
Art Unit(s) | 2833, 2839 |
Total Applications | 3028 |
Issued Applications | 2661 |
Pending Applications | 105 |
Abandoned Applications | 260 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3828293
[patent_doc_number] => 05739066
[patent_country] => US
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[patent_issue_date] => 1998-04-14
[patent_title] => 'Semiconductor processing methods of forming a conductive gate and line'
[patent_app_type] => 1
[patent_app_number] => 8/710353
[patent_app_country] => US
[patent_app_date] => 1996-09-17
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[pdf_file] => patents/05/739/05739066.pdf
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Array
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[patent_doc_number] => 05723370
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[patent_issue_date] => 1998-03-03
[patent_title] => 'FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures'
[patent_app_type] => 1
[patent_app_number] => 8/713061
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[patent_app_date] => 1996-09-12
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[firstpage_image] =>[orig_patent_app_number] => 713061
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/713061 | FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures | Sep 11, 1996 | Issued |
Array
(
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[patent_doc_number] => 05817560
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[patent_issue_date] => 1998-10-06
[patent_title] => 'Ultra short trench transistors and process for making same'
[patent_app_type] => 1
[patent_app_number] => 8/713281
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[patent_app_date] => 1996-09-12
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Array
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[patent_issue_date] => 1998-10-27
[patent_title] => 'Apparatus for electrolytic treatment of an electrolytic solution'
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[patent_app_number] => 8/716821
[patent_app_country] => US
[patent_app_date] => 1996-09-10
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Array
(
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[patent_issue_date] => 1997-09-09
[patent_title] => 'Method for removing metal contained in solution using surfactant having chelating ability'
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Array
(
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[patent_title] => 'Integrated circuit scribe line structures and methods for making same'
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[firstpage_image] =>[orig_patent_app_number] => 699492
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/699492 | Integrated circuit scribe line structures and methods for making same | Aug 18, 1996 | Issued |
Array
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[id] => 3860085
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[patent_issue_date] => 1998-11-17
[patent_title] => 'Methods of fabricating dendritic powder materials for high conductivity paste applications'
[patent_app_type] => 1
[patent_app_number] => 8/689553
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[patent_app_date] => 1996-08-09
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[pdf_file] => patents/05/837/05837119.pdf
[firstpage_image] =>[orig_patent_app_number] => 689553
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/689553 | Methods of fabricating dendritic powder materials for high conductivity paste applications | Aug 8, 1996 | Issued |
Array
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[patent_issue_date] => 1998-03-31
[patent_title] => 'Anodizing apparatus and an anodizing method'
[patent_app_type] => 1
[patent_app_number] => 8/694210
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[pdf_file] => patents/05/733/05733420.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/694210 | Anodizing apparatus and an anodizing method | Aug 7, 1996 | Issued |
Array
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[id] => 3877502
[patent_doc_number] => 05804497
[patent_country] => US
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[patent_issue_date] => 1998-09-08
[patent_title] => 'Selectively doped channel region for increased I.sub.Dsat and method for making same'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/695101 | Selectively doped channel region for increased I.sub.Dsat and method for making same | Aug 6, 1996 | Issued |
Array
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[id] => 3828033
[patent_doc_number] => 05739047
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[patent_issue_date] => 1998-04-14
[patent_title] => 'Method of fabricating a voidless IC electrical plug'
[patent_app_type] => 1
[patent_app_number] => 8/691313
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[patent_app_date] => 1996-08-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/691313 | Method of fabricating a voidless IC electrical plug | Aug 1, 1996 | Issued |
Array
(
[id] => 3697025
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[patent_title] => 'Method for fabricating a mosfet device, with local channel doping and a titanium silicide gate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/691287 | Method for fabricating a mosfet device, with local channel doping and a titanium silicide gate | Jul 31, 1996 | Issued |
Array
(
[id] => 3786040
[patent_doc_number] => 05736445
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[patent_title] => 'Method for producing at least two transsistors in a semiconductor body'
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Array
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[id] => 3730135
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[patent_title] => 'Etch stop for copper damascene process'
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Array
(
[id] => 3791631
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Array
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Array
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[id] => 3681021
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/653928 | Electroformed multilayer flow regulator incorporating force-generating means for selectively constricting the fluid flow path, and a process for the preparation thereof | May 21, 1996 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/651979 | Metal plug with adhesion layer | May 20, 1996 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/633322 | Process for selective application of solder to circuit packages | Apr 16, 1996 | Issued |