Search

Jeffery Shawn Zweizig

Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2849, 2816, 2842, 2504
Total Applications
2645
Issued Applications
2451
Pending Applications
87
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7643322 [patent_doc_number] => 06429720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'RMS-DC converter using a variable gain amplifier to drive a squaring cell' [patent_app_type] => B1 [patent_app_number] => 09/569544 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 8392 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429720.pdf [firstpage_image] =>[orig_patent_app_number] => 09569544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/569544
RMS-DC converter using a variable gain amplifier to drive a squaring cell May 11, 2000 Issued
Array ( [id] => 4389078 [patent_doc_number] => 06294934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Current control technique' [patent_app_type] => 1 [patent_app_number] => 9/559115 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6409 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294934.pdf [firstpage_image] =>[orig_patent_app_number] => 559115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559115
Current control technique Apr 25, 2000 Issued
Array ( [id] => 4425325 [patent_doc_number] => 06225841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Semiconductor device using complementary clock and signal input state detection circuit used for the same' [patent_app_type] => 1 [patent_app_number] => 9/556948 [patent_app_country] => US [patent_app_date] => 2000-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 43 [patent_no_of_words] => 13817 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225841.pdf [firstpage_image] =>[orig_patent_app_number] => 556948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/556948
Semiconductor device using complementary clock and signal input state detection circuit used for the same Apr 20, 2000 Issued
Array ( [id] => 4296672 [patent_doc_number] => 06211720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Logic circuit' [patent_app_type] => 1 [patent_app_number] => 9/551237 [patent_app_country] => US [patent_app_date] => 2000-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 46 [patent_no_of_words] => 11692 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211720.pdf [firstpage_image] =>[orig_patent_app_number] => 551237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/551237
Logic circuit Apr 16, 2000 Issued
Array ( [id] => 4192504 [patent_doc_number] => 06160431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Power-on reset circuit for dual supply voltages' [patent_app_type] => 1 [patent_app_number] => 9/547576 [patent_app_country] => US [patent_app_date] => 2000-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6626 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160431.pdf [firstpage_image] =>[orig_patent_app_number] => 547576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/547576
Power-on reset circuit for dual supply voltages Apr 11, 2000 Issued
Array ( [id] => 4320552 [patent_doc_number] => 06316989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Cascade current miller circuit' [patent_app_type] => 1 [patent_app_number] => 9/543419 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4183 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316989.pdf [firstpage_image] =>[orig_patent_app_number] => 543419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543419
Cascade current miller circuit Apr 4, 2000 Issued
Array ( [id] => 4294340 [patent_doc_number] => 06268758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Circuit arrangement with half-bridge' [patent_app_type] => 1 [patent_app_number] => 9/542339 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2324 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268758.pdf [firstpage_image] =>[orig_patent_app_number] => 542339 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542339
Circuit arrangement with half-bridge Apr 4, 2000 Issued
Array ( [id] => 4392089 [patent_doc_number] => 06262612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Using storage elements with multiple delay values to reduce supply current spikes in digital circuits' [patent_app_type] => 1 [patent_app_number] => 9/543401 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262612.pdf [firstpage_image] =>[orig_patent_app_number] => 543401 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543401
Using storage elements with multiple delay values to reduce supply current spikes in digital circuits Apr 4, 2000 Issued
Array ( [id] => 1566756 [patent_doc_number] => 06339353 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Input circuit of a memory having a lower current dissipation' [patent_app_type] => B1 [patent_app_number] => 09/542454 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 9660 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339353.pdf [firstpage_image] =>[orig_patent_app_number] => 09542454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542454
Input circuit of a memory having a lower current dissipation Apr 3, 2000 Issued
Array ( [id] => 5886385 [patent_doc_number] => 20020011882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Power-on reset signal preparing circuit' [patent_app_type] => new [patent_app_number] => 09/538228 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3731 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20020011882.pdf [firstpage_image] =>[orig_patent_app_number] => 09538228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538228
Power-on reset signal preparing circuit Mar 29, 2000 Issued
Array ( [id] => 4388015 [patent_doc_number] => 06304134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'High-frequency boost technique' [patent_app_type] => 1 [patent_app_number] => 9/537636 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2441 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304134.pdf [firstpage_image] =>[orig_patent_app_number] => 537636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537636
High-frequency boost technique Mar 28, 2000 Issued
Array ( [id] => 4312436 [patent_doc_number] => 06326832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Full swing power down buffer with multiple power supply isolation for standard CMOS processes' [patent_app_type] => 1 [patent_app_number] => 9/537314 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5136 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326832.pdf [firstpage_image] =>[orig_patent_app_number] => 537314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/537314
Full swing power down buffer with multiple power supply isolation for standard CMOS processes Mar 28, 2000 Issued
Array ( [id] => 4378848 [patent_doc_number] => 06288585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor device using external power voltage for timing sensitive signals' [patent_app_type] => 1 [patent_app_number] => 9/535745 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7479 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288585.pdf [firstpage_image] =>[orig_patent_app_number] => 535745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535745
Semiconductor device using external power voltage for timing sensitive signals Mar 26, 2000 Issued
Array ( [id] => 4361669 [patent_doc_number] => 06292049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Circuit and method for reducing voltage oscillations on a digital integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/535057 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2009 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292049.pdf [firstpage_image] =>[orig_patent_app_number] => 535057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535057
Circuit and method for reducing voltage oscillations on a digital integrated circuit Mar 23, 2000 Issued
Array ( [id] => 4312421 [patent_doc_number] => 06326831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Level shift circuit' [patent_app_type] => 1 [patent_app_number] => 9/517154 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6481 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326831.pdf [firstpage_image] =>[orig_patent_app_number] => 517154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/517154
Level shift circuit Mar 1, 2000 Issued
Array ( [id] => 4277644 [patent_doc_number] => 06307407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Driving circuit and charging pump booster circuit utilizing said driving circuit' [patent_app_type] => 1 [patent_app_number] => 9/516545 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3777 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307407.pdf [firstpage_image] =>[orig_patent_app_number] => 516545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516545
Driving circuit and charging pump booster circuit utilizing said driving circuit Feb 29, 2000 Issued
Array ( [id] => 1433612 [patent_doc_number] => 06340902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Semiconductor device having multiple power-supply nodes and capable of self-detecting power-off to prevent erroneous operation' [patent_app_type] => B1 [patent_app_number] => 09/516780 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7912 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340902.pdf [firstpage_image] =>[orig_patent_app_number] => 09516780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516780
Semiconductor device having multiple power-supply nodes and capable of self-detecting power-off to prevent erroneous operation Feb 29, 2000 Issued
Array ( [id] => 1464160 [patent_doc_number] => 06351172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'High-speed output driver with an impedance adjustment scheme' [patent_app_type] => B1 [patent_app_number] => 09/515220 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6505 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351172.pdf [firstpage_image] =>[orig_patent_app_number] => 09515220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515220
High-speed output driver with an impedance adjustment scheme Feb 28, 2000 Issued
Array ( [id] => 4391968 [patent_doc_number] => 06262603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'RC calibration circuit with reduced power consumption and increased accuracy' [patent_app_type] => 1 [patent_app_number] => 9/515183 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 5136 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262603.pdf [firstpage_image] =>[orig_patent_app_number] => 515183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515183
RC calibration circuit with reduced power consumption and increased accuracy Feb 28, 2000 Issued
Array ( [id] => 1537560 [patent_doc_number] => 06337598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Reference voltage generating device and generating method of the same' [patent_app_type] => B1 [patent_app_number] => 09/515543 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3047 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337598.pdf [firstpage_image] =>[orig_patent_app_number] => 09515543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515543
Reference voltage generating device and generating method of the same Feb 28, 2000 Issued
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