Jeffery Shawn Zweizig

Array ( [id] => 4327284 [patent_doc_number] => 06331799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Bias circuit for control input of power transistor' [patent_app_type] => 1 [patent_app_number] => 9/502469 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4653 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331799.pdf [firstpage_image] =>[orig_patent_app_number] => 502469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4412942 [patent_doc_number] => 06232823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Voltage setting circuit in a semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/500638 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7113 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232823.pdf [firstpage_image] =>[orig_patent_app_number] => 500638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425367 [patent_doc_number] => 06225857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Non-inverting driver circuit for low-dropout voltage regulator' [patent_app_type] => 1 [patent_app_number] => 9/499706 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2709 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225857.pdf [firstpage_image] =>[orig_patent_app_number] => 499706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4415412 [patent_doc_number] => 06300820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Voltage regulated charge pump' [patent_app_type] => 1 [patent_app_number] => 9/498699 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4227 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300820.pdf [firstpage_image] =>[orig_patent_app_number] => 498699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363120 [patent_doc_number] => 06201420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Electronic driver circuit that utilizes resonance with load circuitry in combination with timed switching to reduce power consumption' [patent_app_type] => 1 [patent_app_number] => 9/498408 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 8525 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201420.pdf [firstpage_image] =>[orig_patent_app_number] => 498408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326927 [patent_doc_number] => 06249175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Self-biasing circuit' [patent_app_type] => 1 [patent_app_number] => 9/496461 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2721 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249175.pdf [firstpage_image] =>[orig_patent_app_number] => 496461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4300059 [patent_doc_number] => 06236262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Regulated power supply with a high input noise rejection ratio' [patent_app_type] => 1 [patent_app_number] => 9/494002 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1392 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236262.pdf [firstpage_image] =>[orig_patent_app_number] => 494002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1537541 [patent_doc_number] => 06337593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/492506 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 12782 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337593.pdf [firstpage_image] =>[orig_patent_app_number] => 09492506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4415313 [patent_doc_number] => 06300810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Voltage down converter with switched hysteresis' [patent_app_type] => 1 [patent_app_number] => 9/492727 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3118 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300810.pdf [firstpage_image] =>[orig_patent_app_number] => 492727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4353591 [patent_doc_number] => 06285242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Reference voltage shifter' [patent_app_type] => 1 [patent_app_number] => 9/492730 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2124 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285242.pdf [firstpage_image] =>[orig_patent_app_number] => 492730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4416315 [patent_doc_number] => 06229376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Electronic array and methods' [patent_app_type] => 1 [patent_app_number] => 9/478651 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 46 [patent_no_of_words] => 12386 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229376.pdf [firstpage_image] =>[orig_patent_app_number] => 478651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4334147 [patent_doc_number] => 06329863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Input circuit having a fuse therein and semiconductor device having the same' [patent_app_type] => 1 [patent_app_number] => 9/477235 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3002 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329863.pdf [firstpage_image] =>[orig_patent_app_number] => 477235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4268338 [patent_doc_number] => 06259300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Differential input interface circuit and method for adjusting DC levels of differential input signals' [patent_app_type] => 1 [patent_app_number] => 9/477143 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3474 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259300.pdf [firstpage_image] =>[orig_patent_app_number] => 477143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4285125 [patent_doc_number] => 06281734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Reference voltage adjustment' [patent_app_type] => 1 [patent_app_number] => 9/476036 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2794 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281734.pdf [firstpage_image] =>[orig_patent_app_number] => 476036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6138670 [patent_doc_number] => 20020000870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'VOLTAGE BLOCKING METHOD AND APPARATUS FOR A CHARGE PUMP WITH DIODE CONNECTED PULL-UP AND PULL-DOWN ON BOOT NODES' [patent_app_type] => new [patent_app_number] => 09/475459 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4909 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000870.pdf [firstpage_image] =>[orig_patent_app_number] => 09475459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1426139 [patent_doc_number] => 06515534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Enhanced conductivity body biased PMOS driver' [patent_app_type] => B2 [patent_app_number] => 09/475648 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515534.pdf [firstpage_image] =>[orig_patent_app_number] => 09475648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4268395 [patent_doc_number] => 06259304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Real-time standby voltage adjustment circuit' [patent_app_type] => 1 [patent_app_number] => 9/472786 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1675 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259304.pdf [firstpage_image] =>[orig_patent_app_number] => 472786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4378943 [patent_doc_number] => 06288591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Level shifter for multiple supply voltage circuitry' [patent_app_type] => 1 [patent_app_number] => 9/473366 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3096 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288591.pdf [firstpage_image] =>[orig_patent_app_number] => 473366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425370 [patent_doc_number] => 06225858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Performance driven multi-valued variable supply voltage scheme for low power design of VLSI circuits and systems' [patent_app_type] => 1 [patent_app_number] => 9/473897 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2753 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225858.pdf [firstpage_image] =>[orig_patent_app_number] => 473897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4296862 [patent_doc_number] => RE037232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Delay circuit device' [patent_app_type] => 2 [patent_app_number] => 9/460563 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 18160 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/037/RE037232.pdf [firstpage_image] =>[orig_patent_app_number] => 460563 [rel_patent_id] =>[rel_patent_doc_number] =>)