Search

Jeffery Shawn Zweizig

Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2849, 2816, 2842, 2504
Total Applications
2645
Issued Applications
2451
Pending Applications
87
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4326927 [patent_doc_number] => 06249175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Self-biasing circuit' [patent_app_type] => 1 [patent_app_number] => 9/496461 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2721 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249175.pdf [firstpage_image] =>[orig_patent_app_number] => 496461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496461
Self-biasing circuit Feb 1, 2000 Issued
Array ( [id] => 4300059 [patent_doc_number] => 06236262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Regulated power supply with a high input noise rejection ratio' [patent_app_type] => 1 [patent_app_number] => 9/494002 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1392 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236262.pdf [firstpage_image] =>[orig_patent_app_number] => 494002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494002
Regulated power supply with a high input noise rejection ratio Jan 27, 2000 Issued
Array ( [id] => 1537541 [patent_doc_number] => 06337593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/492506 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 12782 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337593.pdf [firstpage_image] =>[orig_patent_app_number] => 09492506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492506
Semiconductor integrated circuit Jan 26, 2000 Issued
Array ( [id] => 4353591 [patent_doc_number] => 06285242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Reference voltage shifter' [patent_app_type] => 1 [patent_app_number] => 9/492730 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2124 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285242.pdf [firstpage_image] =>[orig_patent_app_number] => 492730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492730
Reference voltage shifter Jan 26, 2000 Issued
Array ( [id] => 4415313 [patent_doc_number] => 06300810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Voltage down converter with switched hysteresis' [patent_app_type] => 1 [patent_app_number] => 9/492727 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3118 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300810.pdf [firstpage_image] =>[orig_patent_app_number] => 492727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492727
Voltage down converter with switched hysteresis Jan 26, 2000 Issued
Array ( [id] => 4416315 [patent_doc_number] => 06229376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Electronic array and methods' [patent_app_type] => 1 [patent_app_number] => 9/478651 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 46 [patent_no_of_words] => 12386 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229376.pdf [firstpage_image] =>[orig_patent_app_number] => 478651 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478651
Electronic array and methods Jan 5, 2000 Issued
Array ( [id] => 4334147 [patent_doc_number] => 06329863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Input circuit having a fuse therein and semiconductor device having the same' [patent_app_type] => 1 [patent_app_number] => 9/477235 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3002 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329863.pdf [firstpage_image] =>[orig_patent_app_number] => 477235 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477235
Input circuit having a fuse therein and semiconductor device having the same Jan 3, 2000 Issued
Array ( [id] => 4268338 [patent_doc_number] => 06259300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Differential input interface circuit and method for adjusting DC levels of differential input signals' [patent_app_type] => 1 [patent_app_number] => 9/477143 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3474 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259300.pdf [firstpage_image] =>[orig_patent_app_number] => 477143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477143
Differential input interface circuit and method for adjusting DC levels of differential input signals Jan 2, 2000 Issued
Array ( [id] => 4285125 [patent_doc_number] => 06281734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Reference voltage adjustment' [patent_app_type] => 1 [patent_app_number] => 9/476036 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2794 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281734.pdf [firstpage_image] =>[orig_patent_app_number] => 476036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476036
Reference voltage adjustment Dec 30, 1999 Issued
Array ( [id] => 1426139 [patent_doc_number] => 06515534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Enhanced conductivity body biased PMOS driver' [patent_app_type] => B2 [patent_app_number] => 09/475648 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515534.pdf [firstpage_image] =>[orig_patent_app_number] => 09475648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475648
Enhanced conductivity body biased PMOS driver Dec 29, 1999 Issued
Array ( [id] => 6138670 [patent_doc_number] => 20020000870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'VOLTAGE BLOCKING METHOD AND APPARATUS FOR A CHARGE PUMP WITH DIODE CONNECTED PULL-UP AND PULL-DOWN ON BOOT NODES' [patent_app_type] => new [patent_app_number] => 09/475459 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4909 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000870.pdf [firstpage_image] =>[orig_patent_app_number] => 09475459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475459
Voltage blocking method and apparatus for a charge pump with diode connected pull-up and pull-down on boot nodes Dec 29, 1999 Issued
Array ( [id] => 4425370 [patent_doc_number] => 06225858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Performance driven multi-valued variable supply voltage scheme for low power design of VLSI circuits and systems' [patent_app_type] => 1 [patent_app_number] => 9/473897 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2753 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225858.pdf [firstpage_image] =>[orig_patent_app_number] => 473897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473897
Performance driven multi-valued variable supply voltage scheme for low power design of VLSI circuits and systems Dec 27, 1999 Issued
Array ( [id] => 4268395 [patent_doc_number] => 06259304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Real-time standby voltage adjustment circuit' [patent_app_type] => 1 [patent_app_number] => 9/472786 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1675 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259304.pdf [firstpage_image] =>[orig_patent_app_number] => 472786 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472786
Real-time standby voltage adjustment circuit Dec 27, 1999 Issued
Array ( [id] => 4378943 [patent_doc_number] => 06288591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Level shifter for multiple supply voltage circuitry' [patent_app_type] => 1 [patent_app_number] => 9/473366 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3096 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288591.pdf [firstpage_image] =>[orig_patent_app_number] => 473366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473366
Level shifter for multiple supply voltage circuitry Dec 27, 1999 Issued
Array ( [id] => 4296862 [patent_doc_number] => RE037232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Delay circuit device' [patent_app_type] => 2 [patent_app_number] => 9/460563 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 18160 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/037/RE037232.pdf [firstpage_image] =>[orig_patent_app_number] => 460563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460563
Delay circuit device Dec 13, 1999 Issued
Array ( [id] => 4403235 [patent_doc_number] => 06297673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Evaluation circuit for electronic signal transmitters' [patent_app_type] => 1 [patent_app_number] => 9/423989 [patent_app_country] => US [patent_app_date] => 1999-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1716 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297673.pdf [firstpage_image] =>[orig_patent_app_number] => 423989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/423989
Evaluation circuit for electronic signal transmitters Nov 16, 1999 Issued
Array ( [id] => 4165558 [patent_doc_number] => 06157251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method and apparatus for clock uncertainty minimization' [patent_app_type] => 1 [patent_app_number] => 9/439918 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3823 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157251.pdf [firstpage_image] =>[orig_patent_app_number] => 439918 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439918
Method and apparatus for clock uncertainty minimization Nov 11, 1999 Issued
Array ( [id] => 4267423 [patent_doc_number] => 06204712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method and apparatus for clock uncertainty minimization' [patent_app_type] => 1 [patent_app_number] => 9/439077 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3824 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204712.pdf [firstpage_image] =>[orig_patent_app_number] => 439077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439077
Method and apparatus for clock uncertainty minimization Nov 11, 1999 Issued
Array ( [id] => 4365528 [patent_doc_number] => 06169443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Transmission gate' [patent_app_type] => 1 [patent_app_number] => 9/436632 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7157 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169443.pdf [firstpage_image] =>[orig_patent_app_number] => 436632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436632
Transmission gate Nov 8, 1999 Issued
Array ( [id] => 4390437 [patent_doc_number] => 06278317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Charge pump system having multiple charging rates and corresponding method' [patent_app_type] => 1 [patent_app_number] => 9/430807 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4567 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278317.pdf [firstpage_image] =>[orig_patent_app_number] => 430807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430807
Charge pump system having multiple charging rates and corresponding method Oct 28, 1999 Issued
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