
Jeffery Shawn Zweizig
Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2849, 2816, 2842, 2504 |
| Total Applications | 2645 |
| Issued Applications | 2451 |
| Pending Applications | 87 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4284341
[patent_doc_number] => RE037445
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Modular microscope system'
[patent_app_type] => 2
[patent_app_number] => 9/212295
[patent_app_country] => US
[patent_app_date] => 1998-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 3766
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/037/RE037445.pdf
[firstpage_image] =>[orig_patent_app_number] => 212295
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/212295 | Modular microscope system | Dec 15, 1998 | Issued |
Array
(
[id] => 4245188
[patent_doc_number] => 06144243
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Method and circuit arrangement for reducing offset voltage of a signal'
[patent_app_type] => 1
[patent_app_number] => 9/117751
[patent_app_country] => US
[patent_app_date] => 1998-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 3807
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144243.pdf
[firstpage_image] =>[orig_patent_app_number] => 117751
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/117751 | Method and circuit arrangement for reducing offset voltage of a signal | Oct 8, 1998 | Issued |
Array
(
[id] => 4304220
[patent_doc_number] => 06198338
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Method of constructing a fuse for a semiconductor device and circuit using same'
[patent_app_type] => 1
[patent_app_number] => 9/161228
[patent_app_country] => US
[patent_app_date] => 1998-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2169
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[pdf_file] => patents/06/198/06198338.pdf
[firstpage_image] =>[orig_patent_app_number] => 161228
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/161228 | Method of constructing a fuse for a semiconductor device and circuit using same | Sep 27, 1998 | Issued |
Array
(
[id] => 4163998
[patent_doc_number] => 06107844
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Methods and apparatus for reducing MOSFET body diode conduction in a half-bridge configuration'
[patent_app_type] => 1
[patent_app_number] => 9/162243
[patent_app_country] => US
[patent_app_date] => 1998-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 4051
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[pdf_file] => patents/06/107/06107844.pdf
[firstpage_image] =>[orig_patent_app_number] => 162243
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/162243 | Methods and apparatus for reducing MOSFET body diode conduction in a half-bridge configuration | Sep 27, 1998 | Issued |
Array
(
[id] => 4412891
[patent_doc_number] => 06232818
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-15
[patent_title] => 'Voltage translator'
[patent_app_type] => 1
[patent_app_number] => 9/158723
[patent_app_country] => US
[patent_app_date] => 1998-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5411
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/232/06232818.pdf
[firstpage_image] =>[orig_patent_app_number] => 158723
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/158723 | Voltage translator | Sep 21, 1998 | Issued |
Array
(
[id] => 4192712
[patent_doc_number] => 06094077
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Dynamically controlled timing signal generator'
[patent_app_type] => 1
[patent_app_number] => 9/156320
[patent_app_country] => US
[patent_app_date] => 1998-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 3314
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/094/06094077.pdf
[firstpage_image] =>[orig_patent_app_number] => 156320
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/156320 | Dynamically controlled timing signal generator | Sep 17, 1998 | Issued |
Array
(
[id] => 4257036
[patent_doc_number] => 06222397
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Output circuit with switching function'
[patent_app_type] => 1
[patent_app_number] => 9/154807
[patent_app_country] => US
[patent_app_date] => 1998-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 11725
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/222/06222397.pdf
[firstpage_image] =>[orig_patent_app_number] => 154807
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/154807 | Output circuit with switching function | Sep 16, 1998 | Issued |
Array
(
[id] => 931531
[patent_doc_number] => 06980037
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-27
[patent_title] => 'Power on reset techniques for an integrated circuit chip'
[patent_app_type] => utility
[patent_app_number] => 09/153864
[patent_app_country] => US
[patent_app_date] => 1998-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
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[patent_no_of_words] => 14496
[patent_no_of_claims] => 17
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/980/06980037.pdf
[firstpage_image] =>[orig_patent_app_number] => 09153864
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153864 | Power on reset techniques for an integrated circuit chip | Sep 15, 1998 | Issued |
Array
(
[id] => 4198091
[patent_doc_number] => 06130575
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-10
[patent_title] => 'High-speed switching regulator drive circuit'
[patent_app_type] => 1
[patent_app_number] => 9/153108
[patent_app_country] => US
[patent_app_date] => 1998-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 8221
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/130/06130575.pdf
[firstpage_image] =>[orig_patent_app_number] => 153108
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153108 | High-speed switching regulator drive circuit | Sep 14, 1998 | Issued |
Array
(
[id] => 4224486
[patent_doc_number] => 06111439
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'High-speed switching regulator drive circuit'
[patent_app_type] => 1
[patent_app_number] => 9/153111
[patent_app_country] => US
[patent_app_date] => 1998-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 8215
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/111/06111439.pdf
[firstpage_image] =>[orig_patent_app_number] => 153111
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153111 | High-speed switching regulator drive circuit | Sep 14, 1998 | Issued |
Array
(
[id] => 4141827
[patent_doc_number] => 06121800
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Impedance matched, voltage-mode H-bridge write drivers'
[patent_app_type] => 1
[patent_app_number] => 9/152869
[patent_app_country] => US
[patent_app_date] => 1998-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 3788
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/121/06121800.pdf
[firstpage_image] =>[orig_patent_app_number] => 152869
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/152869 | Impedance matched, voltage-mode H-bridge write drivers | Sep 13, 1998 | Issued |
| 08/894741 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH DELAY ERROR CORRECTING CIRCUIT | Sep 9, 1998 | Abandoned |
Array
(
[id] => 4245090
[patent_doc_number] => 06144238
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Integrated power-on-reset circuit'
[patent_app_type] => 1
[patent_app_number] => 9/151156
[patent_app_country] => US
[patent_app_date] => 1998-09-10
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[pdf_file] => patents/06/144/06144238.pdf
[firstpage_image] =>[orig_patent_app_number] => 151156
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/151156 | Integrated power-on-reset circuit | Sep 9, 1998 | Issued |
Array
(
[id] => 4367184
[patent_doc_number] => 06191633
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Semiconductor integrated circuit with protection circuit against electrostatic discharge'
[patent_app_type] => 1
[patent_app_number] => 9/149115
[patent_app_country] => US
[patent_app_date] => 1998-09-09
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[pdf_file] => patents/06/191/06191633.pdf
[firstpage_image] =>[orig_patent_app_number] => 149115
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/149115 | Semiconductor integrated circuit with protection circuit against electrostatic discharge | Sep 8, 1998 | Issued |
Array
(
[id] => 4179181
[patent_doc_number] => 06140859
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Analog switch comprising connected bipolar junction transistors'
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[patent_app_number] => 9/148264
[patent_app_country] => US
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[pdf_file] => patents/06/140/06140859.pdf
[firstpage_image] =>[orig_patent_app_number] => 148264
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/148264 | Analog switch comprising connected bipolar junction transistors | Sep 3, 1998 | Issued |
Array
(
[id] => 4245047
[patent_doc_number] => 06144235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Control circuit for a motor-operated switch'
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[patent_app_number] => 9/143916
[patent_app_country] => US
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[pdf_file] => patents/06/144/06144235.pdf
[firstpage_image] =>[orig_patent_app_number] => 143916
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143916 | Control circuit for a motor-operated switch | Aug 30, 1998 | Issued |
Array
(
[id] => 4412201
[patent_doc_number] => 06271694
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Monolithically integrated output stage'
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[patent_app_number] => 9/143235
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[pdf_file] => patents/06/271/06271694.pdf
[firstpage_image] =>[orig_patent_app_number] => 143235
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143235 | Monolithically integrated output stage | Aug 27, 1998 | Issued |
Array
(
[id] => 4424130
[patent_doc_number] => 06194950
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'High-speed CMOS multiplexer'
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[patent_app_number] => 9/143170
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[pdf_file] => patents/06/194/06194950.pdf
[firstpage_image] =>[orig_patent_app_number] => 143170
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143170 | High-speed CMOS multiplexer | Aug 27, 1998 | Issued |
Array
(
[id] => 4104173
[patent_doc_number] => 06097229
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[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Bus-hold circuit having low leakage when power is off'
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[patent_app_number] => 9/143702
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[pdf_file] => patents/06/097/06097229.pdf
[firstpage_image] =>[orig_patent_app_number] => 143702
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143702 | Bus-hold circuit having low leakage when power is off | Aug 27, 1998 | Issued |
Array
(
[id] => 4141880
[patent_doc_number] => 06121804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'High frequency CMOS clock recovery circuit'
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[patent_app_number] => 9/140840
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[pdf_file] => patents/06/121/06121804.pdf
[firstpage_image] =>[orig_patent_app_number] => 140840
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140840 | High frequency CMOS clock recovery circuit | Aug 26, 1998 | Issued |