Search

Jeffery Shawn Zweizig

Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2849, 2816, 2842, 2504
Total Applications
2645
Issued Applications
2451
Pending Applications
87
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4089040 [patent_doc_number] => 06054892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Timing circuit' [patent_app_type] => 1 [patent_app_number] => 9/112103 [patent_app_country] => US [patent_app_date] => 1998-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1675 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054892.pdf [firstpage_image] =>[orig_patent_app_number] => 112103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112103
Timing circuit Jul 7, 1998 Issued
Array ( [id] => 4225401 [patent_doc_number] => 06087877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Integrated circuit having surge protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/110332 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8159 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087877.pdf [firstpage_image] =>[orig_patent_app_number] => 110332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/110332
Integrated circuit having surge protection circuit Jul 5, 1998 Issued
Array ( [id] => 4110570 [patent_doc_number] => 06052012 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method and apparatus for clock uncertainly minimization' [patent_app_type] => 1 [patent_app_number] => 9/106823 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3820 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052012.pdf [firstpage_image] =>[orig_patent_app_number] => 106823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106823
Method and apparatus for clock uncertainly minimization Jun 28, 1998 Issued
Array ( [id] => 4214216 [patent_doc_number] => 06028461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Clock adjusting circuit and method to adjust a delay value of a clock input signal' [patent_app_type] => 1 [patent_app_number] => 9/105136 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3014 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028461.pdf [firstpage_image] =>[orig_patent_app_number] => 105136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105136
Clock adjusting circuit and method to adjust a delay value of a clock input signal Jun 25, 1998 Issued
Array ( [id] => 4058652 [patent_doc_number] => 05969569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Process for controlling at least one IGBT type transistor enabling its operation under irradiation' [patent_app_type] => 1 [patent_app_number] => 9/095584 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4713 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969569.pdf [firstpage_image] =>[orig_patent_app_number] => 095584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095584
Process for controlling at least one IGBT type transistor enabling its operation under irradiation Jun 10, 1998 Issued
Array ( [id] => 4115362 [patent_doc_number] => 06057719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Programmable, self-resetting divider' [patent_app_type] => 1 [patent_app_number] => 9/092412 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057719.pdf [firstpage_image] =>[orig_patent_app_number] => 092412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092412
Programmable, self-resetting divider Jun 4, 1998 Issued
Array ( [id] => 3991900 [patent_doc_number] => 05959477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Precision power-on reset circuit' [patent_app_type] => 1 [patent_app_number] => 9/088828 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6313 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959477.pdf [firstpage_image] =>[orig_patent_app_number] => 088828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088828
Precision power-on reset circuit Jun 1, 1998 Issued
Array ( [id] => 4110488 [patent_doc_number] => 06052006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Current mirror triggered power-on-reset circuit' [patent_app_type] => 1 [patent_app_number] => 9/085444 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7302 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052006.pdf [firstpage_image] =>[orig_patent_app_number] => 085444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085444
Current mirror triggered power-on-reset circuit May 26, 1998 Issued
Array ( [id] => 4245948 [patent_doc_number] => 06081151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Electronically controlled variable attenuator' [patent_app_type] => 1 [patent_app_number] => 9/083166 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2069 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081151.pdf [firstpage_image] =>[orig_patent_app_number] => 083166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083166
Electronically controlled variable attenuator May 21, 1998 Issued
09/082314 ZERO DC CURRENT POWER-ON RESET CIRCUIT May 19, 1998 Abandoned
Array ( [id] => 4164112 [patent_doc_number] => 06107852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method and device for the reduction of latch insertion delay' [patent_app_type] => 1 [patent_app_number] => 9/081001 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2805 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107852.pdf [firstpage_image] =>[orig_patent_app_number] => 081001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081001
Method and device for the reduction of latch insertion delay May 18, 1998 Issued
Array ( [id] => 4164099 [patent_doc_number] => 06107851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Offline converter with integrated softstart and frequency jitter' [patent_app_type] => 1 [patent_app_number] => 9/080774 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6781 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107851.pdf [firstpage_image] =>[orig_patent_app_number] => 080774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080774
Offline converter with integrated softstart and frequency jitter May 17, 1998 Issued
Array ( [id] => 4255914 [patent_doc_number] => 06137330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Integrated circuit including functional blocks controlled by common synchronizing control transistors' [patent_app_type] => 1 [patent_app_number] => 9/080258 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4851 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137330.pdf [firstpage_image] =>[orig_patent_app_number] => 080258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080258
Integrated circuit including functional blocks controlled by common synchronizing control transistors May 17, 1998 Issued
Array ( [id] => 4111122 [patent_doc_number] => 06100746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Electrically programmable fuse' [patent_app_type] => 1 [patent_app_number] => 9/080115 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2466 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100746.pdf [firstpage_image] =>[orig_patent_app_number] => 080115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080115
Electrically programmable fuse May 17, 1998 Issued
Array ( [id] => 4141938 [patent_doc_number] => 06121808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'DLL calibrated phase multiplexer and interpolator' [patent_app_type] => 1 [patent_app_number] => 9/080860 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4419 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121808.pdf [firstpage_image] =>[orig_patent_app_number] => 080860 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080860
DLL calibrated phase multiplexer and interpolator May 17, 1998 Issued
Array ( [id] => 4160872 [patent_doc_number] => 06124749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Semiconductor circuit device with reduced power consumption' [patent_app_type] => 1 [patent_app_number] => 9/080259 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7352 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124749.pdf [firstpage_image] =>[orig_patent_app_number] => 080259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080259
Semiconductor circuit device with reduced power consumption May 17, 1998 Issued
Array ( [id] => 4186647 [patent_doc_number] => 06037812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Delay locked loop (DLL) based clock synthesis' [patent_app_type] => 1 [patent_app_number] => 9/080623 [patent_app_country] => US [patent_app_date] => 1998-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3888 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037812.pdf [firstpage_image] =>[orig_patent_app_number] => 080623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/080623
Delay locked loop (DLL) based clock synthesis May 17, 1998 Issued
Array ( [id] => 4225299 [patent_doc_number] => 06087870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Output circuit which switches an output state in accordance with a timing signal and a delay signal of the timing signal' [patent_app_type] => 1 [patent_app_number] => 9/078758 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 17045 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087870.pdf [firstpage_image] =>[orig_patent_app_number] => 078758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/078758
Output circuit which switches an output state in accordance with a timing signal and a delay signal of the timing signal May 14, 1998 Issued
Array ( [id] => 3955714 [patent_doc_number] => 05999023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Clock forwarding circuit in semiconductor integrated circuit and clock forwarding method' [patent_app_type] => 1 [patent_app_number] => 9/078940 [patent_app_country] => US [patent_app_date] => 1998-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2780 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999023.pdf [firstpage_image] =>[orig_patent_app_number] => 078940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/078940
Clock forwarding circuit in semiconductor integrated circuit and clock forwarding method May 13, 1998 Issued
Array ( [id] => 4163889 [patent_doc_number] => 06104225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor device using complementary clock and signal input state detection circuit used for the same' [patent_app_type] => 1 [patent_app_number] => 9/076810 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 43 [patent_no_of_words] => 13819 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104225.pdf [firstpage_image] =>[orig_patent_app_number] => 076810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076810
Semiconductor device using complementary clock and signal input state detection circuit used for the same May 12, 1998 Issued
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