
Jeffery Shawn Zweizig
Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2849, 2816, 2842, 2504 |
| Total Applications | 2645 |
| Issued Applications | 2451 |
| Pending Applications | 87 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4110357
[patent_doc_number] => 06051997
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Circuit for tracking rapid changes in mid-point voltage of a data signal'
[patent_app_type] => 1
[patent_app_number] => 9/076412
[patent_app_country] => US
[patent_app_date] => 1998-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3100
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/051/06051997.pdf
[firstpage_image] =>[orig_patent_app_number] => 076412
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/076412 | Circuit for tracking rapid changes in mid-point voltage of a data signal | May 11, 1998 | Issued |
Array
(
[id] => 3963355
[patent_doc_number] => 05936442
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Power shut-off and recovery circuit for data communication devices'
[patent_app_type] => 1
[patent_app_number] => 9/071558
[patent_app_country] => US
[patent_app_date] => 1998-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4104
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/936/05936442.pdf
[firstpage_image] =>[orig_patent_app_number] => 071558
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071558 | Power shut-off and recovery circuit for data communication devices | Apr 30, 1998 | Issued |
Array
(
[id] => 4226337
[patent_doc_number] => 06040722
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-21
[patent_title] => 'Power-on reset circuit with adjustable interval'
[patent_app_type] => 1
[patent_app_number] => 9/071518
[patent_app_country] => US
[patent_app_date] => 1998-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 1914
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/040/06040722.pdf
[firstpage_image] =>[orig_patent_app_number] => 071518
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071518 | Power-on reset circuit with adjustable interval | Apr 30, 1998 | Issued |
Array
(
[id] => 4241588
[patent_doc_number] => 06118321
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Pass transistor capacitive coupling control circuit'
[patent_app_type] => 1
[patent_app_number] => 9/067107
[patent_app_country] => US
[patent_app_date] => 1998-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2610
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/118/06118321.pdf
[firstpage_image] =>[orig_patent_app_number] => 067107
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/067107 | Pass transistor capacitive coupling control circuit | Apr 26, 1998 | Issued |
Array
(
[id] => 4106383
[patent_doc_number] => 06066968
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Delay lock loop circuit for semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/065909
[patent_app_country] => US
[patent_app_date] => 1998-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1299
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/066/06066968.pdf
[firstpage_image] =>[orig_patent_app_number] => 065909
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/065909 | Delay lock loop circuit for semiconductor memory device | Apr 23, 1998 | Issued |
Array
(
[id] => 4142083
[patent_doc_number] => 06121815
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Semiconductor integrated circuit, system, and method for reducing a skew between a clock signal and a data signal'
[patent_app_type] => 1
[patent_app_number] => 9/066234
[patent_app_country] => US
[patent_app_date] => 1998-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 35
[patent_no_of_words] => 14666
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/121/06121815.pdf
[firstpage_image] =>[orig_patent_app_number] => 066234
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/066234 | Semiconductor integrated circuit, system, and method for reducing a skew between a clock signal and a data signal | Apr 23, 1998 | Issued |
Array
(
[id] => 4189501
[patent_doc_number] => 06020778
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Transmission gate including body effect compensation circuit'
[patent_app_type] => 1
[patent_app_number] => 9/064814
[patent_app_country] => US
[patent_app_date] => 1998-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7158
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/020/06020778.pdf
[firstpage_image] =>[orig_patent_app_number] => 064814
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/064814 | Transmission gate including body effect compensation circuit | Apr 22, 1998 | Issued |
| 09/064999 | CLOCK BUFFER CIRCUIT HAVING SHORT PROPAGATION DELAY | Apr 22, 1998 | Abandoned |
Array
(
[id] => 4115389
[patent_doc_number] => 06057721
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Reference circuit using current feedback for fast biasing upon power-up'
[patent_app_type] => 1
[patent_app_number] => 9/065003
[patent_app_country] => US
[patent_app_date] => 1998-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2288
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/057/06057721.pdf
[firstpage_image] =>[orig_patent_app_number] => 065003
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/065003 | Reference circuit using current feedback for fast biasing upon power-up | Apr 22, 1998 | Issued |
Array
(
[id] => 4058453
[patent_doc_number] => 05969555
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Pulse width forming circuit'
[patent_app_type] => 1
[patent_app_number] => 9/063281
[patent_app_country] => US
[patent_app_date] => 1998-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3949
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/969/05969555.pdf
[firstpage_image] =>[orig_patent_app_number] => 063281
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/063281 | Pulse width forming circuit | Apr 19, 1998 | Issued |
Array
(
[id] => 4092532
[patent_doc_number] => 06025744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Glitch free delay line multiplexing technique'
[patent_app_type] => 1
[patent_app_number] => 9/062415
[patent_app_country] => US
[patent_app_date] => 1998-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2308
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/025/06025744.pdf
[firstpage_image] =>[orig_patent_app_number] => 062415
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/062415 | Glitch free delay line multiplexing technique | Apr 16, 1998 | Issued |
Array
(
[id] => 4088866
[patent_doc_number] => 06054880
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Circuit with high-voltage output stage'
[patent_app_type] => 1
[patent_app_number] => 9/059172
[patent_app_country] => US
[patent_app_date] => 1998-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 5037
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/054/06054880.pdf
[firstpage_image] =>[orig_patent_app_number] => 059172
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/059172 | Circuit with high-voltage output stage | Apr 12, 1998 | Issued |
Array
(
[id] => 4040626
[patent_doc_number] => 05942922
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Inhibitable, continuously-terminated differential drive circuit for an integrated circuit tester'
[patent_app_type] => 1
[patent_app_number] => 9/056543
[patent_app_country] => US
[patent_app_date] => 1998-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/942/05942922.pdf
[firstpage_image] =>[orig_patent_app_number] => 056543
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/056543 | Inhibitable, continuously-terminated differential drive circuit for an integrated circuit tester | Apr 6, 1998 | Issued |
Array
(
[id] => 3941147
[patent_doc_number] => 05939909
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Driver circuit having preslewing circuitry for improved slew rate control'
[patent_app_type] => 1
[patent_app_number] => 9/052187
[patent_app_country] => US
[patent_app_date] => 1998-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 13047
[patent_no_of_claims] => 30
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[patent_words_short_claim] => 715
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/939/05939909.pdf
[firstpage_image] =>[orig_patent_app_number] => 052187
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/052187 | Driver circuit having preslewing circuitry for improved slew rate control | Mar 30, 1998 | Issued |
| 09/052840 | OPEN DRAIN PAD DRIVER HAVING POWER-ON AND POWER-OFF PROTECTION FROM PAD VOLTAGES | Mar 30, 1998 | Abandoned |
Array
(
[id] => 4112689
[patent_doc_number] => 06023176
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Input buffer'
[patent_app_type] => 1
[patent_app_number] => 9/049823
[patent_app_country] => US
[patent_app_date] => 1998-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3346
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/023/06023176.pdf
[firstpage_image] =>[orig_patent_app_number] => 049823
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/049823 | Input buffer | Mar 26, 1998 | Issued |
Array
(
[id] => 4211826
[patent_doc_number] => 06078205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Circuit device, drive circuit, and display apparatus including these components'
[patent_app_type] => 1
[patent_app_number] => 9/048176
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[patent_app_date] => 1998-03-26
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[pdf_file] => patents/06/078/06078205.pdf
[firstpage_image] =>[orig_patent_app_number] => 048176
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/048176 | Circuit device, drive circuit, and display apparatus including these components | Mar 25, 1998 | Issued |
Array
(
[id] => 4092818
[patent_doc_number] => 06018257
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Output drive circuit tolerant of higher voltage signals'
[patent_app_type] => 1
[patent_app_number] => 9/046781
[patent_app_country] => US
[patent_app_date] => 1998-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018257.pdf
[firstpage_image] =>[orig_patent_app_number] => 046781
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/046781 | Output drive circuit tolerant of higher voltage signals | Mar 22, 1998 | Issued |
Array
(
[id] => 4139716
[patent_doc_number] => 06147528
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Method of invoking a power-down mode on an integrated circuit by monitoring a normally changing input signal'
[patent_app_type] => 1
[patent_app_number] => 9/041937
[patent_app_country] => US
[patent_app_date] => 1998-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/147/06147528.pdf
[firstpage_image] =>[orig_patent_app_number] => 041937
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/041937 | Method of invoking a power-down mode on an integrated circuit by monitoring a normally changing input signal | Mar 12, 1998 | Issued |
Array
(
[id] => 4199699
[patent_doc_number] => 06043688
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Ratio metric fault tolerant and redundant serial communication system'
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[patent_app_number] => 9/038581
[patent_app_country] => US
[patent_app_date] => 1998-03-11
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[pdf_file] => patents/06/043/06043688.pdf
[firstpage_image] =>[orig_patent_app_number] => 038581
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/038581 | Ratio metric fault tolerant and redundant serial communication system | Mar 10, 1998 | Issued |