
Jeffery Shawn Zweizig
Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2849, 2816, 2842, 2504 |
| Total Applications | 2645 |
| Issued Applications | 2451 |
| Pending Applications | 87 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4211731
[patent_doc_number] => 06078198
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Device and method for driving a capacitive actuator'
[patent_app_type] => 1
[patent_app_number] => 9/038639
[patent_app_country] => US
[patent_app_date] => 1998-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3641
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/078/06078198.pdf
[firstpage_image] =>[orig_patent_app_number] => 038639
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/038639 | Device and method for driving a capacitive actuator | Mar 9, 1998 | Issued |
Array
(
[id] => 4179038
[patent_doc_number] => 06140848
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Electronic driver circuit that utilizes resonance with load circuitry in combination with timed switching to reduce power consumption'
[patent_app_type] => 1
[patent_app_number] => 9/029707
[patent_app_country] => US
[patent_app_date] => 1998-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 8584
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/140/06140848.pdf
[firstpage_image] =>[orig_patent_app_number] => 029707
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/029707 | Electronic driver circuit that utilizes resonance with load circuitry in combination with timed switching to reduce power consumption | Mar 5, 1998 | Issued |
Array
(
[id] => 4058538
[patent_doc_number] => 05969561
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-19
[patent_title] => 'Integrated circuit having a variable RF resistor'
[patent_app_type] => 1
[patent_app_number] => 9/035368
[patent_app_country] => US
[patent_app_date] => 1998-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5137
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/969/05969561.pdf
[firstpage_image] =>[orig_patent_app_number] => 035368
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/035368 | Integrated circuit having a variable RF resistor | Mar 4, 1998 | Issued |
Array
(
[id] => 4229584
[patent_doc_number] => 06011424
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Integrated birectional transistor switch for large signal voltages'
[patent_app_type] => 1
[patent_app_number] => 9/033740
[patent_app_country] => US
[patent_app_date] => 1998-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3832
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/011/06011424.pdf
[firstpage_image] =>[orig_patent_app_number] => 033740
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/033740 | Integrated birectional transistor switch for large signal voltages | Mar 2, 1998 | Issued |
Array
(
[id] => 4000915
[patent_doc_number] => 05920224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Network for improving electro-magnetic interference response'
[patent_app_type] => 1
[patent_app_number] => 9/024203
[patent_app_country] => US
[patent_app_date] => 1998-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 7165
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/920/05920224.pdf
[firstpage_image] =>[orig_patent_app_number] => 024203
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/024203 | Network for improving electro-magnetic interference response | Feb 16, 1998 | Issued |
Array
(
[id] => 4246434
[patent_doc_number] => 06091274
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Optimum placement of bypass capacitors in a network for improving electro-magnetic interference response'
[patent_app_type] => 1
[patent_app_number] => 9/024099
[patent_app_country] => US
[patent_app_date] => 1998-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 7224
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/091/06091274.pdf
[firstpage_image] =>[orig_patent_app_number] => 024099
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/024099 | Optimum placement of bypass capacitors in a network for improving electro-magnetic interference response | Feb 16, 1998 | Issued |
Array
(
[id] => 4225170
[patent_doc_number] => 06087861
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Data network drivers including balanced current supplies and related methods'
[patent_app_type] => 1
[patent_app_number] => 9/023020
[patent_app_country] => US
[patent_app_date] => 1998-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4749
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/087/06087861.pdf
[firstpage_image] =>[orig_patent_app_number] => 023020
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/023020 | Data network drivers including balanced current supplies and related methods | Feb 10, 1998 | Issued |
Array
(
[id] => 4164291
[patent_doc_number] => 06107863
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Charge pump circuit and logic circuit'
[patent_app_type] => 1
[patent_app_number] => 9/017633
[patent_app_country] => US
[patent_app_date] => 1998-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 25
[patent_no_of_words] => 10925
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/107/06107863.pdf
[firstpage_image] =>[orig_patent_app_number] => 017633
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017633 | Charge pump circuit and logic circuit | Feb 2, 1998 | Issued |
Array
(
[id] => 3965895
[patent_doc_number] => 05900747
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Sampling phase detector'
[patent_app_type] => 1
[patent_app_number] => 9/017427
[patent_app_country] => US
[patent_app_date] => 1998-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1446
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/900/05900747.pdf
[firstpage_image] =>[orig_patent_app_number] => 017427
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/017427 | Sampling phase detector | Feb 1, 1998 | Issued |
Array
(
[id] => 3946737
[patent_doc_number] => 05973534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Dynamic bias circuit for driving low voltage I/O transistors'
[patent_app_type] => 1
[patent_app_number] => 9/015360
[patent_app_country] => US
[patent_app_date] => 1998-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4593
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/973/05973534.pdf
[firstpage_image] =>[orig_patent_app_number] => 015360
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/015360 | Dynamic bias circuit for driving low voltage I/O transistors | Jan 28, 1998 | Issued |
Array
(
[id] => 4019761
[patent_doc_number] => 05963078
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Transformer coupled FET drive circuit'
[patent_app_type] => 1
[patent_app_number] => 9/013132
[patent_app_country] => US
[patent_app_date] => 1998-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2578
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/963/05963078.pdf
[firstpage_image] =>[orig_patent_app_number] => 013132
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/013132 | Transformer coupled FET drive circuit | Jan 25, 1998 | Issued |
Array
(
[id] => 3992067
[patent_doc_number] => 05959488
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Dual-node capacitor coupled MOSFET for improving ESD performance'
[patent_app_type] => 1
[patent_app_number] => 9/012928
[patent_app_country] => US
[patent_app_date] => 1998-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2502
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/959/05959488.pdf
[firstpage_image] =>[orig_patent_app_number] => 012928
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/012928 | Dual-node capacitor coupled MOSFET for improving ESD performance | Jan 23, 1998 | Issued |
Array
(
[id] => 4111068
[patent_doc_number] => 06100742
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Driver circuit for slope-controlled pulse switching of a load'
[patent_app_type] => 1
[patent_app_number] => 9/008194
[patent_app_country] => US
[patent_app_date] => 1998-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2777
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/100/06100742.pdf
[firstpage_image] =>[orig_patent_app_number] => 008194
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/008194 | Driver circuit for slope-controlled pulse switching of a load | Jan 14, 1998 | Issued |
| 09/006825 | TRAINING METHOD FOR GM-C OR MOS-C CIRCUITS | Jan 13, 1998 | Issued |
Array
(
[id] => 4088881
[patent_doc_number] => 06054881
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Input/output (I/O) buffer selectively providing resistive termination for a transmission line coupled thereto'
[patent_app_type] => 1
[patent_app_number] => 9/005234
[patent_app_country] => US
[patent_app_date] => 1998-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5762
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/054/06054881.pdf
[firstpage_image] =>[orig_patent_app_number] => 005234
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/005234 | Input/output (I/O) buffer selectively providing resistive termination for a transmission line coupled thereto | Jan 8, 1998 | Issued |
Array
(
[id] => 4211776
[patent_doc_number] => 06078201
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Power-on reset circuit for dual supply voltages'
[patent_app_type] => 1
[patent_app_number] => 9/003474
[patent_app_country] => US
[patent_app_date] => 1998-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 6624
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/078/06078201.pdf
[firstpage_image] =>[orig_patent_app_number] => 003474
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/003474 | Power-on reset circuit for dual supply voltages | Jan 5, 1998 | Issued |
Array
(
[id] => 4365459
[patent_doc_number] => 06169439
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Current limited power MOSFET device with improved safe operating area'
[patent_app_type] => 1
[patent_app_number] => 9/000825
[patent_app_country] => US
[patent_app_date] => 1997-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3283
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/169/06169439.pdf
[firstpage_image] =>[orig_patent_app_number] => 000825
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/000825 | Current limited power MOSFET device with improved safe operating area | Dec 29, 1997 | Issued |
Array
(
[id] => 4375889
[patent_doc_number] => 06275088
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-14
[patent_title] => 'Method and apparatus for dynamic impedance clamping of a digital signal delivered over a transmission line'
[patent_app_type] => 1
[patent_app_number] => 8/999008
[patent_app_country] => US
[patent_app_date] => 1997-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5136
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/275/06275088.pdf
[firstpage_image] =>[orig_patent_app_number] => 999008
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/999008 | Method and apparatus for dynamic impedance clamping of a digital signal delivered over a transmission line | Dec 28, 1997 | Issued |
Array
(
[id] => 4165174
[patent_doc_number] => 06157227
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Device for neutralization in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/993377
[patent_app_country] => US
[patent_app_date] => 1997-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3856
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/157/06157227.pdf
[firstpage_image] =>[orig_patent_app_number] => 993377
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993377 | Device for neutralization in an integrated circuit | Dec 17, 1997 | Issued |
Array
(
[id] => 4284974
[patent_doc_number] => 06281723
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Device and method for power-on/power-off checking of an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/993071
[patent_app_country] => US
[patent_app_date] => 1997-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5486
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/281/06281723.pdf
[firstpage_image] =>[orig_patent_app_number] => 993071
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993071 | Device and method for power-on/power-off checking of an integrated circuit | Dec 17, 1997 | Issued |