
Jeffery Shawn Zweizig
Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2816, 2849, 2842, 2504 |
| Total Applications | 2640 |
| Issued Applications | 2460 |
| Pending Applications | 67 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4059176
[patent_doc_number] => 05933036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Power-on reset signal generating circuit'
[patent_app_type] => 1
[patent_app_number] => 8/887933
[patent_app_country] => US
[patent_app_date] => 1997-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 1991
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/933/05933036.pdf
[firstpage_image] =>[orig_patent_app_number] => 887933
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/887933 | Power-on reset signal generating circuit | Jul 2, 1997 | Issued |
Array
(
[id] => 4040666
[patent_doc_number] => 05942924
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Digital circuit for conserving static current in an electronic device'
[patent_app_type] => 1
[patent_app_number] => 8/886620
[patent_app_country] => US
[patent_app_date] => 1997-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 11
[patent_no_of_words] => 3872
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/942/05942924.pdf
[firstpage_image] =>[orig_patent_app_number] => 886620
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/886620 | Digital circuit for conserving static current in an electronic device | Jun 30, 1997 | Issued |
| 08/886338 | POWER-ON RESET CIRCUIT | Jun 30, 1997 | Abandoned |
Array
(
[id] => 4029073
[patent_doc_number] => 05926050
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Separate set/reset paths for time critical signals'
[patent_app_type] => 1
[patent_app_number] => 8/885145
[patent_app_country] => US
[patent_app_date] => 1997-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4704
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926050.pdf
[firstpage_image] =>[orig_patent_app_number] => 885145
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/885145 | Separate set/reset paths for time critical signals | Jun 29, 1997 | Issued |
Array
(
[id] => 3847481
[patent_doc_number] => 05847596
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Internal voltage generator'
[patent_app_type] => 1
[patent_app_number] => 8/885835
[patent_app_country] => US
[patent_app_date] => 1997-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 2007
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/847/05847596.pdf
[firstpage_image] =>[orig_patent_app_number] => 885835
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/885835 | Internal voltage generator | Jun 29, 1997 | Issued |
Array
(
[id] => 3776888
[patent_doc_number] => 05850160
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Gate drive circuit for an SCR'
[patent_app_type] => 1
[patent_app_number] => 8/877623
[patent_app_country] => US
[patent_app_date] => 1997-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3421
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/850/05850160.pdf
[firstpage_image] =>[orig_patent_app_number] => 877623
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/877623 | Gate drive circuit for an SCR | Jun 17, 1997 | Issued |
Array
(
[id] => 4050410
[patent_doc_number] => 05909141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Step-up potential supply circuit and semiconductor storage device'
[patent_app_type] => 1
[patent_app_number] => 8/874351
[patent_app_country] => US
[patent_app_date] => 1997-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 34
[patent_no_of_words] => 13559
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909141.pdf
[firstpage_image] =>[orig_patent_app_number] => 874351
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/874351 | Step-up potential supply circuit and semiconductor storage device | Jun 12, 1997 | Issued |
Array
(
[id] => 3944643
[patent_doc_number] => 05872468
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Level detector circuit, interface and method for interpreting and processing multi-level signals'
[patent_app_type] => 1
[patent_app_number] => 8/873936
[patent_app_country] => US
[patent_app_date] => 1997-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5240
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/872/05872468.pdf
[firstpage_image] =>[orig_patent_app_number] => 873936
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/873936 | Level detector circuit, interface and method for interpreting and processing multi-level signals | Jun 11, 1997 | Issued |
Array
(
[id] => 3910938
[patent_doc_number] => 05898327
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-27
[patent_title] => 'Low-power reset signal generating circuit improved in voltage rising characteristic'
[patent_app_type] => 1
[patent_app_number] => 8/872387
[patent_app_country] => US
[patent_app_date] => 1997-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3623
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/898/05898327.pdf
[firstpage_image] =>[orig_patent_app_number] => 872387
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/872387 | Low-power reset signal generating circuit improved in voltage rising characteristic | Jun 9, 1997 | Issued |
Array
(
[id] => 4055877
[patent_doc_number] => 05869991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Automatic runaway detector and reset circuit'
[patent_app_type] => 1
[patent_app_number] => 8/870340
[patent_app_country] => US
[patent_app_date] => 1997-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2141
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/869/05869991.pdf
[firstpage_image] =>[orig_patent_app_number] => 870340
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/870340 | Automatic runaway detector and reset circuit | Jun 5, 1997 | Issued |
Array
(
[id] => 3750255
[patent_doc_number] => 05801569
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Output driver for mixed supply voltage systems'
[patent_app_type] => 1
[patent_app_number] => 8/867465
[patent_app_country] => US
[patent_app_date] => 1997-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4069
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/801/05801569.pdf
[firstpage_image] =>[orig_patent_app_number] => 867465
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867465 | Output driver for mixed supply voltage systems | Jun 1, 1997 | Issued |
Array
(
[id] => 3777975
[patent_doc_number] => 05774011
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Antifuse circuit using standard MOSFET devices'
[patent_app_type] => 1
[patent_app_number] => 8/864254
[patent_app_country] => US
[patent_app_date] => 1997-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 2553
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/774/05774011.pdf
[firstpage_image] =>[orig_patent_app_number] => 864254
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/864254 | Antifuse circuit using standard MOSFET devices | May 27, 1997 | Issued |
Array
(
[id] => 3882384
[patent_doc_number] => 05825217
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Low power accelerated switching for MOS circuits'
[patent_app_type] => 1
[patent_app_number] => 8/861173
[patent_app_country] => US
[patent_app_date] => 1997-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2840
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825217.pdf
[firstpage_image] =>[orig_patent_app_number] => 861173
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/861173 | Low power accelerated switching for MOS circuits | May 20, 1997 | Issued |
Array
(
[id] => 3876524
[patent_doc_number] => 05838184
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Equivalent variable resistor circuits'
[patent_app_type] => 1
[patent_app_number] => 8/861198
[patent_app_country] => US
[patent_app_date] => 1997-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7006
[patent_no_of_claims] => 10
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[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/838/05838184.pdf
[firstpage_image] =>[orig_patent_app_number] => 861198
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/861198 | Equivalent variable resistor circuits | May 20, 1997 | Issued |
Array
(
[id] => 3898283
[patent_doc_number] => 05834963
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Circuit configuration for parameter adjustment'
[patent_app_type] => 1
[patent_app_number] => 8/858818
[patent_app_country] => US
[patent_app_date] => 1997-05-19
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2118
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/834/05834963.pdf
[firstpage_image] =>[orig_patent_app_number] => 858818
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/858818 | Circuit configuration for parameter adjustment | May 18, 1997 | Issued |
Array
(
[id] => 3882653
[patent_doc_number] => 05825236
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Low voltage bias circuit for generating supply-independent bias voltages currents'
[patent_app_type] => 1
[patent_app_number] => 8/859798
[patent_app_country] => US
[patent_app_date] => 1997-05-19
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825236.pdf
[firstpage_image] =>[orig_patent_app_number] => 859798
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/859798 | Low voltage bias circuit for generating supply-independent bias voltages currents | May 18, 1997 | Issued |
Array
(
[id] => 3963341
[patent_doc_number] => 05936441
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Clock pulse generator'
[patent_app_type] => 1
[patent_app_number] => 8/857202
[patent_app_country] => US
[patent_app_date] => 1997-05-15
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/936/05936441.pdf
[firstpage_image] =>[orig_patent_app_number] => 857202
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/857202 | Clock pulse generator | May 14, 1997 | Issued |
Array
(
[id] => 3881649
[patent_doc_number] => 05764093
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Variable delay circuit'
[patent_app_type] => 1
[patent_app_number] => 8/850816
[patent_app_country] => US
[patent_app_date] => 1997-05-02
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764093.pdf
[firstpage_image] =>[orig_patent_app_number] => 850816
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850816 | Variable delay circuit | May 1, 1997 | Issued |
Array
(
[id] => 3768745
[patent_doc_number] => 05844434
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Start-up circuit for maximum headroom CMOS devices'
[patent_app_type] => 1
[patent_app_number] => 8/842344
[patent_app_country] => US
[patent_app_date] => 1997-04-24
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[pdf_file] => patents/05/844/05844434.pdf
[firstpage_image] =>[orig_patent_app_number] => 842344
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/842344 | Start-up circuit for maximum headroom CMOS devices | Apr 23, 1997 | Issued |
Array
(
[id] => 4011487
[patent_doc_number] => 05859558
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Low voltage analog front end'
[patent_app_type] => 1
[patent_app_number] => 8/827855
[patent_app_country] => US
[patent_app_date] => 1997-04-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/859/05859558.pdf
[firstpage_image] =>[orig_patent_app_number] => 827855
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/827855 | Low voltage analog front end | Apr 10, 1997 | Issued |