Search

Jeffery Shawn Zweizig

Examiner (ID: 5312, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2842, 2849, 2504
Total Applications
2641
Issued Applications
2460
Pending Applications
70
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5042202 [patent_doc_number] => 20070094484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Backing store buffer for the register save engine of a stacked register file' [patent_app_type] => utility [patent_app_number] => 11/254320 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4899 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094484.pdf [firstpage_image] =>[orig_patent_app_number] => 11254320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254320
Backing store buffer for the register save engine of a stacked register file Oct 19, 2005 Issued
Array ( [id] => 136368 [patent_doc_number] => 07702889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Shared interrupt control method and system for a digital signal processor' [patent_app_type] => utility [patent_app_number] => 11/253906 [patent_app_country] => US [patent_app_date] => 2005-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4528 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/702/07702889.pdf [firstpage_image] =>[orig_patent_app_number] => 11253906 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/253906
Shared interrupt control method and system for a digital signal processor Oct 17, 2005 Issued
Array ( [id] => 87662 [patent_doc_number] => 07743236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Reconfigurable processor' [patent_app_type] => utility [patent_app_number] => 11/244062 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10153 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 440 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743236.pdf [firstpage_image] =>[orig_patent_app_number] => 11244062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/244062
Reconfigurable processor Oct 5, 2005 Issued
Array ( [id] => 5695810 [patent_doc_number] => 20060155957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Encoding method for very long instruction word (VLIW) DSP processor and decoding method thereof' [patent_app_type] => utility [patent_app_number] => 11/242785 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3107 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155957.pdf [firstpage_image] =>[orig_patent_app_number] => 11242785 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242785
Encoding method for very long instruction word (VLIW) DSP processor and decoding method thereof Oct 4, 2005 Abandoned
Array ( [id] => 5108624 [patent_doc_number] => 20070067502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Method for preventing long latency event' [patent_app_type] => utility [patent_app_number] => 11/233590 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1958 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20070067502.pdf [firstpage_image] =>[orig_patent_app_number] => 11233590 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/233590
Method for preventing long latency event Sep 21, 2005 Abandoned
Array ( [id] => 8171075 [patent_doc_number] => 08176481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Methods and apparatus for distributing software applications' [patent_app_type] => utility [patent_app_number] => 11/231131 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 41 [patent_no_of_words] => 21315 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176481.pdf [firstpage_image] =>[orig_patent_app_number] => 11231131 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231131
Methods and apparatus for distributing software applications Sep 19, 2005 Issued
Array ( [id] => 5778482 [patent_doc_number] => 20060107122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Methods and apparatus for emulating software applications' [patent_app_type] => utility [patent_app_number] => 11/230748 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 24110 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20060107122.pdf [firstpage_image] =>[orig_patent_app_number] => 11230748 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/230748
Methods and apparatus for emulating software applications Sep 19, 2005 Abandoned
Array ( [id] => 4581463 [patent_doc_number] => 07840785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Transparent concurrent atomic execution' [patent_app_type] => utility [patent_app_number] => 11/227417 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 6775 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840785.pdf [firstpage_image] =>[orig_patent_app_number] => 11227417 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227417
Transparent concurrent atomic execution Sep 13, 2005 Issued
Array ( [id] => 5195250 [patent_doc_number] => 20070083735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Hierarchical processor' [patent_app_type] => utility [patent_app_number] => 11/215833 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 20571 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083735.pdf [firstpage_image] =>[orig_patent_app_number] => 11215833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215833
Hierarchical processor Aug 28, 2005 Abandoned
Array ( [id] => 5001298 [patent_doc_number] => 20070043932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Wakeup mechanisms for schedulers' [patent_app_type] => utility [patent_app_number] => 11/208916 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4671 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043932.pdf [firstpage_image] =>[orig_patent_app_number] => 11208916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/208916
Wakeup mechanisms for schedulers Aug 21, 2005 Abandoned
Array ( [id] => 5150540 [patent_doc_number] => 20070050600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Preventing loss of traced information in a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/205310 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7203 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20070050600.pdf [firstpage_image] =>[orig_patent_app_number] => 11205310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205310
Preventing loss of traced information in a data processing apparatus Aug 16, 2005 Issued
Array ( [id] => 5001296 [patent_doc_number] => 20070043930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Performance of a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/204399 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6695 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043930.pdf [firstpage_image] =>[orig_patent_app_number] => 11204399 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204399
Performance of a data processing apparatus Aug 15, 2005 Abandoned
Array ( [id] => 5001297 [patent_doc_number] => 20070043931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'System and method for high frequency stall design' [patent_app_type] => utility [patent_app_number] => 11/204414 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043931.pdf [firstpage_image] =>[orig_patent_app_number] => 11204414 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204414
System and method for high frequency stall design Aug 15, 2005 Issued
Array ( [id] => 860406 [patent_doc_number] => 07376817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Partial load/store forward prediction' [patent_app_type] => utility [patent_app_number] => 11/200744 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7896 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376817.pdf [firstpage_image] =>[orig_patent_app_number] => 11200744 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200744
Partial load/store forward prediction Aug 9, 2005 Issued
Array ( [id] => 5809390 [patent_doc_number] => 20060095746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Branch predictor, processor and branch prediction method' [patent_app_type] => utility [patent_app_number] => 11/199235 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9758 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095746.pdf [firstpage_image] =>[orig_patent_app_number] => 11199235 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199235
Branch predictor, processor and branch prediction method Aug 8, 2005 Abandoned
Array ( [id] => 8001165 [patent_doc_number] => 08082430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Representing a plurality of instructions with a fewer number of micro-operations' [patent_app_type] => utility [patent_app_number] => 11/200777 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5101 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082430.pdf [firstpage_image] =>[orig_patent_app_number] => 11200777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200777
Representing a plurality of instructions with a fewer number of micro-operations Aug 8, 2005 Issued
Array ( [id] => 4614154 [patent_doc_number] => 07996659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Microprocessor instruction that allows system routine calls and returns from all contexts' [patent_app_type] => utility [patent_app_number] => 11/145613 [patent_app_country] => US [patent_app_date] => 2005-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4055 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996659.pdf [firstpage_image] =>[orig_patent_app_number] => 11145613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/145613
Microprocessor instruction that allows system routine calls and returns from all contexts Jun 5, 2005 Issued
Array ( [id] => 7057331 [patent_doc_number] => 20050278506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Controller having decoding means' [patent_app_type] => utility [patent_app_number] => 11/132145 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4000 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278506.pdf [firstpage_image] =>[orig_patent_app_number] => 11132145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/132145
Controller having decoding means May 19, 2005 Abandoned
Array ( [id] => 7233188 [patent_doc_number] => 20050262331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Controller and method for processing instructions' [patent_app_type] => utility [patent_app_number] => 11/134612 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2994 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20050262331.pdf [firstpage_image] =>[orig_patent_app_number] => 11134612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/134612
Controller and method for processing instructions May 19, 2005 Abandoned
Array ( [id] => 7690027 [patent_doc_number] => 20070234006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Integrated Circuit and Metod for Issuing Transactions' [patent_app_type] => utility [patent_app_number] => 11/568139 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6354 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234006.pdf [firstpage_image] =>[orig_patent_app_number] => 11568139 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/568139
Integrated Circuit and Metod for Issuing Transactions Apr 11, 2005 Abandoned
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