Search

Jeffery Shawn Zweizig

Examiner (ID: 5312, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2842, 2849, 2504
Total Applications
2641
Issued Applications
2460
Pending Applications
70
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5795025 [patent_doc_number] => 20060015706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'TLB correlated branch predictor and method for use thereof' [patent_app_type] => utility [patent_app_number] => 10/879085 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3964 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015706.pdf [firstpage_image] =>[orig_patent_app_number] => 10879085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/879085
TLB correlated branch predictor and method for use thereof Jun 29, 2004 Abandoned
Array ( [id] => 6946665 [patent_doc_number] => 20050198482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Central processing unit having a micro-code engine' [patent_app_type] => utility [patent_app_number] => 10/875829 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5692 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198482.pdf [firstpage_image] =>[orig_patent_app_number] => 10875829 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875829
Central processing unit having a micro-code engine Jun 23, 2004 Abandoned
Array ( [id] => 6932551 [patent_doc_number] => 20050283586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Stepping a virtual machine guest' [patent_app_type] => utility [patent_app_number] => 10/876092 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2469 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20050283586.pdf [firstpage_image] =>[orig_patent_app_number] => 10876092 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876092
Single stepping a virtual machine guest using a reorder buffer Jun 21, 2004 Issued
Array ( [id] => 5195245 [patent_doc_number] => 20070083730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Data processing device and method' [patent_app_type] => utility [patent_app_number] => 10/561135 [patent_app_country] => US [patent_app_date] => 2004-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 62292 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083730.pdf [firstpage_image] =>[orig_patent_app_number] => 10561135 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/561135
Data processing device and method Jun 16, 2004 Abandoned
Array ( [id] => 355531 [patent_doc_number] => 07493481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-17 [patent_title] => 'Direct hardware processing of internal data structure fields' [patent_app_type] => utility [patent_app_number] => 10/848485 [patent_app_country] => US [patent_app_date] => 2004-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 7633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493481.pdf [firstpage_image] =>[orig_patent_app_number] => 10848485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/848485
Direct hardware processing of internal data structure fields May 16, 2004 Issued
Array ( [id] => 427808 [patent_doc_number] => 07272704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-18 [patent_title] => 'Hardware looping mechanism and method for efficient execution of discontinuity instructions' [patent_app_type] => utility [patent_app_number] => 10/844941 [patent_app_country] => US [patent_app_date] => 2004-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272704.pdf [firstpage_image] =>[orig_patent_app_number] => 10844941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/844941
Hardware looping mechanism and method for efficient execution of discontinuity instructions May 12, 2004 Issued
Array ( [id] => 7021578 [patent_doc_number] => 20050223203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Segmented branch predictor' [patent_app_type] => utility [patent_app_number] => 10/815241 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1365 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20050223203.pdf [firstpage_image] =>[orig_patent_app_number] => 10815241 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815241
Segmented branch predictor Mar 29, 2004 Abandoned
Array ( [id] => 365105 [patent_doc_number] => 07483420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'DSP circuitry for supporting multi-channel applications by selectively shifting data through registers' [patent_app_type] => utility [patent_app_number] => 10/796499 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4949 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/483/07483420.pdf [firstpage_image] =>[orig_patent_app_number] => 10796499 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796499
DSP circuitry for supporting multi-channel applications by selectively shifting data through registers Mar 7, 2004 Issued
Array ( [id] => 6941064 [patent_doc_number] => 20050114627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Co-processing' [patent_app_type] => utility [patent_app_number] => 10/723454 [patent_app_country] => US [patent_app_date] => 2003-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3424 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20050114627.pdf [firstpage_image] =>[orig_patent_app_number] => 10723454 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/723454
Co-processing Nov 25, 2003 Abandoned
Array ( [id] => 7245558 [patent_doc_number] => 20050081015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Method and apparatus for adapting write instructions for an expansion bus' [patent_app_type] => utility [patent_app_number] => 10/677082 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3954 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20050081015.pdf [firstpage_image] =>[orig_patent_app_number] => 10677082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677082
Method and apparatus for adapting write instructions for an expansion bus Sep 29, 2003 Abandoned
Array ( [id] => 7394951 [patent_doc_number] => 20040031022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Information processing device for multiple instruction sets with reconfigurable mechanism' [patent_app_type] => new [patent_app_number] => 10/608015 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5275 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20040031022.pdf [firstpage_image] =>[orig_patent_app_number] => 10608015 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608015
Information processing device for multiple instruction sets with reconfigurable mechanism Jun 29, 2003 Abandoned
Array ( [id] => 7282120 [patent_doc_number] => 20040064497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Method and system of program transmission optimization using a redundant transmission sequence' [patent_app_type] => new [patent_app_number] => 10/361840 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 13592 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064497.pdf [firstpage_image] =>[orig_patent_app_number] => 10361840 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361840
Method and system of program transmission optimization using a redundant transmission sequence Feb 9, 2003 Issued
Array ( [id] => 431378 [patent_doc_number] => 07269719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Predicated execution using operand predicates' [patent_app_type] => utility [patent_app_number] => 10/283709 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269719.pdf [firstpage_image] =>[orig_patent_app_number] => 10283709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283709
Predicated execution using operand predicates Oct 29, 2002 Issued
Array ( [id] => 6804266 [patent_doc_number] => 20030231660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Bit-manipulation instructions for packet processing' [patent_app_type] => new [patent_app_number] => 10/172196 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9051 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20030231660.pdf [firstpage_image] =>[orig_patent_app_number] => 10172196 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/172196
Bit-manipulation instructions for packet processing Jun 13, 2002 Abandoned
Array ( [id] => 8170774 [patent_doc_number] => 08176296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Programmable microcontroller architecture' [patent_app_type] => utility [patent_app_number] => 10/033027 [patent_app_country] => US [patent_app_date] => 2001-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 36 [patent_no_of_words] => 18292 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176296.pdf [firstpage_image] =>[orig_patent_app_number] => 10033027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033027
Programmable microcontroller architecture Oct 21, 2001 Issued
Array ( [id] => 48687 [patent_doc_number] => 07779236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-17 [patent_title] => 'Symbolic store-load bypass' [patent_app_type] => utility [patent_app_number] => 09/443160 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2497 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/779/07779236.pdf [firstpage_image] =>[orig_patent_app_number] => 09443160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/443160
Symbolic store-load bypass Nov 18, 1999 Issued
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