Search

Jeffery Shawn Zweizig

Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2849, 2816, 2842, 2504
Total Applications
2645
Issued Applications
2451
Pending Applications
87
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18676863 [patent_doc_number] => 20230314496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => BROADBAND LOSSLESS PARTIAL DISCHARGE DETECTION AND NOISE REMOVAL DEVICE [patent_app_type] => utility [patent_app_number] => 18/016159 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18016159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/016159
Broadband lossless partial discharge detection and noise removal device Jul 14, 2020 Issued
Array ( [id] => 17164592 [patent_doc_number] => 11150687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-19 [patent_title] => Low-latency retimer with seamless clock switchover [patent_app_type] => utility [patent_app_number] => 16/926614 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6603 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926614
Low-latency retimer with seamless clock switchover Jul 9, 2020 Issued
Array ( [id] => 17347769 [patent_doc_number] => 20220014100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => MULTIPHASE VOLTAGE REGULATOR WITH MULTIPLE VOLTAGE SENSING LOCATIONS [patent_app_type] => utility [patent_app_number] => 16/923648 [patent_app_country] => US [patent_app_date] => 2020-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923648 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/923648
Multiphase voltage regulator with multiple voltage sensing locations Jul 7, 2020 Issued
Array ( [id] => 18639414 [patent_doc_number] => 11764033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => High voltage power supply [patent_app_type] => utility [patent_app_number] => 17/623687 [patent_app_country] => US [patent_app_date] => 2020-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4095 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17623687 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/623687
High voltage power supply Jul 2, 2020 Issued
Array ( [id] => 16881703 [patent_doc_number] => 11031865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Charge pump circuit configured for positive and negative voltage generation [patent_app_type] => utility [patent_app_number] => 16/911967 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6406 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911967 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911967
Charge pump circuit configured for positive and negative voltage generation Jun 24, 2020 Issued
Array ( [id] => 17303883 [patent_doc_number] => 20210399722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => SYMMETRICALLY-INTERCONNECTED TUNABLE TIME DELAY CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/906501 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906501 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906501
Symmetrically-interconnected tunable time delay circuit Jun 18, 2020 Issued
Array ( [id] => 17559780 [patent_doc_number] => 11316509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-26 [patent_title] => Maintaining safe operating area operation of transistors during ramp up [patent_app_type] => utility [patent_app_number] => 16/906347 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3276 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906347
Maintaining safe operating area operation of transistors during ramp up Jun 18, 2020 Issued
Array ( [id] => 17122592 [patent_doc_number] => 11133741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Power supply device [patent_app_type] => utility [patent_app_number] => 16/905294 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6142 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905294
Power supply device Jun 17, 2020 Issued
Array ( [id] => 17284555 [patent_doc_number] => 11201603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Active clamp capacitor balancing [patent_app_type] => utility [patent_app_number] => 16/905469 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8140 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905469 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905469
Active clamp capacitor balancing Jun 17, 2020 Issued
Array ( [id] => 18387763 [patent_doc_number] => 11658560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Energy supply system for feeding a DC link, and method for operating the system [patent_app_type] => utility [patent_app_number] => 17/625978 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3962 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17625978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/625978
Energy supply system for feeding a DC link, and method for operating the system Jun 16, 2020 Issued
Array ( [id] => 16528621 [patent_doc_number] => 20200402702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => DATA AND POWER ISOLATION BARRIER [patent_app_type] => utility [patent_app_number] => 16/903618 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903618
Data and power isolation barrier Jun 16, 2020 Issued
Array ( [id] => 17033379 [patent_doc_number] => 11095202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Method and apparatus for common-mode voltage cancellation [patent_app_type] => utility [patent_app_number] => 16/902920 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902920 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902920
Method and apparatus for common-mode voltage cancellation Jun 15, 2020 Issued
Array ( [id] => 16615438 [patent_doc_number] => 20210034091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => Reference Voltage Generation Circuit [patent_app_type] => utility [patent_app_number] => 16/903365 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903365 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903365
Reference voltage generation circuit Jun 15, 2020 Issued
Array ( [id] => 16803854 [patent_doc_number] => 10998816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => On-chip determination of charge pump efficiency using a current limiter [patent_app_type] => utility [patent_app_number] => 16/899428 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899428
On-chip determination of charge pump efficiency using a current limiter Jun 10, 2020 Issued
Array ( [id] => 16835798 [patent_doc_number] => 11012061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-18 [patent_title] => Self-calibrating low-noise duty cycle correction circuit and method thereof [patent_app_type] => utility [patent_app_number] => 16/896364 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16896364 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/896364
Self-calibrating low-noise duty cycle correction circuit and method thereof Jun 8, 2020 Issued
Array ( [id] => 17075923 [patent_doc_number] => 11112315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Blending temperature-dependent currents to generate bias current with temperature dependent profile [patent_app_type] => utility [patent_app_number] => 16/897086 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 10334 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897086 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/897086
Blending temperature-dependent currents to generate bias current with temperature dependent profile Jun 8, 2020 Issued
Array ( [id] => 16739618 [patent_doc_number] => 10965292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-30 [patent_title] => Delay-locked loop device and operation method therefor [patent_app_type] => utility [patent_app_number] => 16/896206 [patent_app_country] => US [patent_app_date] => 2020-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3183 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16896206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/896206
Delay-locked loop device and operation method therefor Jun 7, 2020 Issued
Array ( [id] => 16818376 [patent_doc_number] => 11003200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-11 [patent_title] => Closed loop junction temperature regulation [patent_app_type] => utility [patent_app_number] => 16/893818 [patent_app_country] => US [patent_app_date] => 2020-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16893818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/893818
Closed loop junction temperature regulation Jun 4, 2020 Issued
Array ( [id] => 16737353 [patent_doc_number] => 10963002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-30 [patent_title] => Clock generation architecture using a poly-phase filter with self-correction capability [patent_app_type] => utility [patent_app_number] => 16/890820 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890820
Clock generation architecture using a poly-phase filter with self-correction capability Jun 1, 2020 Issued
Array ( [id] => 16856606 [patent_doc_number] => 20210157351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => BANDGAP REFERENCE VOLTAGE GENERATING CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/887002 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887002
Bandgap reference voltage generating circuit May 28, 2020 Issued
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