Jeffery Shawn Zweizig

Array ( [id] => 4512087 [patent_doc_number] => 07915951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-29 [patent_title] => 'Locally calibrated current source' [patent_app_type] => utility [patent_app_number] => 12/610358 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 992 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915951.pdf [firstpage_image] =>[orig_patent_app_number] => 12610358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6306189 [patent_doc_number] => 20100109760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'VOLTAGE BOOSTING CIRCUIT AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/610601 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3919 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109760.pdf [firstpage_image] =>[orig_patent_app_number] => 12610601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4610914 [patent_doc_number] => 07994847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-09 [patent_title] => 'Reduced gain variation biasing for short channel devices' [patent_app_type] => utility [patent_app_number] => 12/606746 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/994/07994847.pdf [firstpage_image] =>[orig_patent_app_number] => 12606746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15033 [patent_doc_number] => 07804348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-28 [patent_title] => 'Clock data recovery with high speed level shift' [patent_app_type] => utility [patent_app_number] => 12/603231 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5182 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/804/07804348.pdf [firstpage_image] =>[orig_patent_app_number] => 12603231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4504541 [patent_doc_number] => 07920021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Method of applying wire voltage to semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/580299 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6048 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/920/07920021.pdf [firstpage_image] =>[orig_patent_app_number] => 12580299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4458149 [patent_doc_number] => 07893754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-22 [patent_title] => 'Temperature independent reference circuit' [patent_app_type] => utility [patent_app_number] => 12/587204 [patent_app_country] => US [patent_app_date] => 2009-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2496 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893754.pdf [firstpage_image] =>[orig_patent_app_number] => 12587204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4434237 [patent_doc_number] => 07969239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Charge pump circuit and a novel capacitor for a memory integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/569832 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5674 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969239.pdf [firstpage_image] =>[orig_patent_app_number] => 12569832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6522467 [patent_doc_number] => 20100123517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'GATE-CONTROLLED RECTIFIER AND APPLICATION TO RECTIFICATION CIRCUITS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/569298 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3454 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123517.pdf [firstpage_image] =>[orig_patent_app_number] => 12569298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4601170 [patent_doc_number] => 07978006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Quantum interference transistors and methods of manufacturing and operating the same' [patent_app_type] => utility [patent_app_number] => 12/585724 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978006.pdf [firstpage_image] =>[orig_patent_app_number] => 12585724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6524738 [patent_doc_number] => 20100231289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'CMOS BIAS CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/563575 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20100231289.pdf [firstpage_image] =>[orig_patent_app_number] => 12563575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500977 [patent_doc_number] => 07948307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Dual dielectric tri-gate field effect transistor' [patent_app_type] => utility [patent_app_number] => 12/561880 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3222 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948307.pdf [firstpage_image] =>[orig_patent_app_number] => 12561880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4446426 [patent_doc_number] => 07863966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-04 [patent_title] => 'Readout circuit for touch panel' [patent_app_type] => utility [patent_app_number] => 12/561857 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3752 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863966.pdf [firstpage_image] =>[orig_patent_app_number] => 12561857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4489967 [patent_doc_number] => 07884664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Input device, and multi-function peripheral' [patent_app_type] => utility [patent_app_number] => 12/550194 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10562 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884664.pdf [firstpage_image] =>[orig_patent_app_number] => 12550194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4480360 [patent_doc_number] => 07906996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-15 [patent_title] => 'System and method for controlling an integrated circuit in different operational modes' [patent_app_type] => utility [patent_app_number] => 12/543467 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/906/07906996.pdf [firstpage_image] =>[orig_patent_app_number] => 12543467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4434224 [patent_doc_number] => 07969231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Internal voltage generating circuit' [patent_app_type] => utility [patent_app_number] => 12/497090 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5697 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969231.pdf [firstpage_image] =>[orig_patent_app_number] => 12497090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6287360 [patent_doc_number] => 20100237930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'INTERNAL VOLTAGE GENERATING APPARATUS AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/494437 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6172 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237930.pdf [firstpage_image] =>[orig_patent_app_number] => 12494437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5395536 [patent_doc_number] => 20090315599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'CIRCUIT WITH A REGULATED CHARGE PUMP' [patent_app_type] => utility [patent_app_number] => 12/490062 [patent_app_country] => US [patent_app_date] => 2009-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3218 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315599.pdf [firstpage_image] =>[orig_patent_app_number] => 12490062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6576628 [patent_doc_number] => 20100321100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'NEGATIVE ANALOG SWITCH DESIGN' [patent_app_type] => utility [patent_app_number] => 12/488287 [patent_app_country] => US [patent_app_date] => 2009-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20100321100.pdf [firstpage_image] =>[orig_patent_app_number] => 12488287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5462196 [patent_doc_number] => 20090322396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'CIRCUIT TO REDUCE DUTY CYCLE DISTORTION' [patent_app_type] => utility [patent_app_number] => 12/486579 [patent_app_country] => US [patent_app_date] => 2009-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6961 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0322/20090322396.pdf [firstpage_image] =>[orig_patent_app_number] => 12486579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 83261 [patent_doc_number] => 07746149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Voltage level shift circuit and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/484664 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6232 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746149.pdf [firstpage_image] =>[orig_patent_app_number] => 12484664 [rel_patent_id] =>[rel_patent_doc_number] =>)