Search

Jeffery Shawn Zweizig

Examiner (ID: 5312, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2842, 2849, 2504
Total Applications
2641
Issued Applications
2460
Pending Applications
70
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 268558 [patent_doc_number] => 07568087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Partial load/store forward prediction' [patent_app_type] => utility [patent_app_number] => 12/055016 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7925 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/568/07568087.pdf [firstpage_image] =>[orig_patent_app_number] => 12055016 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055016
Partial load/store forward prediction Mar 24, 2008 Issued
Array ( [id] => 4712895 [patent_doc_number] => 20080301421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Method of speeding up execution of repeatable commands and microcontroller able to speed up execution of repeatable commands' [patent_app_type] => utility [patent_app_number] => 12/076879 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3011 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20080301421.pdf [firstpage_image] =>[orig_patent_app_number] => 12076879 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076879
Method of speeding up execution of repeatable commands and microcontroller able to speed up execution of repeatable commands Mar 24, 2008 Abandoned
Array ( [id] => 5405616 [patent_doc_number] => 20090240931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'Indirect Function Call Instructions in a Synchronous Parallel Thread Processor' [patent_app_type] => utility [patent_app_number] => 12/054255 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20090240931.pdf [firstpage_image] =>[orig_patent_app_number] => 12054255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054255
Indirect function call instructions in a synchronous parallel thread processor Mar 23, 2008 Issued
Array ( [id] => 8235486 [patent_doc_number] => 08200947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-12 [patent_title] => 'Systems and methods for voting among parallel threads' [patent_app_type] => utility [patent_app_number] => 12/054322 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8847 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/200/08200947.pdf [firstpage_image] =>[orig_patent_app_number] => 12054322 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054322
Systems and methods for voting among parallel threads Mar 23, 2008 Issued
Array ( [id] => 7779875 [patent_doc_number] => 08122228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Broadcasting collective operation contributions throughout a parallel computer' [patent_app_type] => utility [patent_app_number] => 12/053842 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11195 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122228.pdf [firstpage_image] =>[orig_patent_app_number] => 12053842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053842
Broadcasting collective operation contributions throughout a parallel computer Mar 23, 2008 Issued
Array ( [id] => 4600637 [patent_doc_number] => 07984272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Design structure for single hot forward interconnect scheme for delayed execution pipelines' [patent_app_type] => utility [patent_app_number] => 12/052959 [patent_app_country] => US [patent_app_date] => 2008-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7748 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984272.pdf [firstpage_image] =>[orig_patent_app_number] => 12052959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/052959
Design structure for single hot forward interconnect scheme for delayed execution pipelines Mar 20, 2008 Issued
Array ( [id] => 4512535 [patent_doc_number] => 07921279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Operand and result forwarding between differently sized operands in a superscalar processor' [patent_app_type] => utility [patent_app_number] => 12/051792 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3315 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/921/07921279.pdf [firstpage_image] =>[orig_patent_app_number] => 12051792 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051792
Operand and result forwarding between differently sized operands in a superscalar processor Mar 18, 2008 Issued
Array ( [id] => 316905 [patent_doc_number] => 07526638 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-28 [patent_title] => 'Hardware alteration of instructions in a microcode routine' [patent_app_type] => utility [patent_app_number] => 12/049340 [patent_app_country] => US [patent_app_date] => 2008-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2884 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526638.pdf [firstpage_image] =>[orig_patent_app_number] => 12049340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/049340
Hardware alteration of instructions in a microcode routine Mar 15, 2008 Issued
Array ( [id] => 7510398 [patent_doc_number] => 08037287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Error recovery following speculative execution with an instruction processing pipeline' [patent_app_type] => utility [patent_app_number] => 12/076165 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5655 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037287.pdf [firstpage_image] =>[orig_patent_app_number] => 12076165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076165
Error recovery following speculative execution with an instruction processing pipeline Mar 13, 2008 Issued
Array ( [id] => 4868962 [patent_doc_number] => 20080148021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'High Frequency Stall Design' [patent_app_type] => utility [patent_app_number] => 12/036704 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6327 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148021.pdf [firstpage_image] =>[orig_patent_app_number] => 12036704 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036704
High Frequency Stall Design Feb 24, 2008 Abandoned
Array ( [id] => 8208003 [patent_doc_number] => 08190855 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-29 [patent_title] => 'Coupling data for interrupt processing in a parallel processing environment' [patent_app_type] => utility [patent_app_number] => 12/036918 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 26255 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/190/08190855.pdf [firstpage_image] =>[orig_patent_app_number] => 12036918 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036918
Coupling data for interrupt processing in a parallel processing environment Feb 24, 2008 Issued
Array ( [id] => 5393363 [patent_doc_number] => 20090210676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'System and Method for the Scheduling of Load Instructions Within a Group Priority Issue Schema for a Cascaded Pipeline' [patent_app_type] => utility [patent_app_number] => 12/033085 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210676.pdf [firstpage_image] =>[orig_patent_app_number] => 12033085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033085
System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline Feb 18, 2008 Issued
Array ( [id] => 4486510 [patent_doc_number] => 07870368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'System and method for prioritizing branch instructions' [patent_app_type] => utility [patent_app_number] => 12/033127 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8000 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870368.pdf [firstpage_image] =>[orig_patent_app_number] => 12033127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033127
System and method for prioritizing branch instructions Feb 18, 2008 Issued
Array ( [id] => 4448948 [patent_doc_number] => 07865700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'System and method for prioritizing store instructions' [patent_app_type] => utility [patent_app_number] => 12/033052 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8481 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865700.pdf [firstpage_image] =>[orig_patent_app_number] => 12033052 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033052
System and method for prioritizing store instructions Feb 18, 2008 Issued
Array ( [id] => 4614149 [patent_doc_number] => 07996654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'System and method for optimization within a group priority issue schema for a cascaded pipeline' [patent_app_type] => utility [patent_app_number] => 12/033100 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7584 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996654.pdf [firstpage_image] =>[orig_patent_app_number] => 12033100 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033100
System and method for optimization within a group priority issue schema for a cascaded pipeline Feb 18, 2008 Issued
Array ( [id] => 4600635 [patent_doc_number] => 07984270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'System and method for prioritizing arithmetic instructions' [patent_app_type] => utility [patent_app_number] => 12/033047 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8305 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984270.pdf [firstpage_image] =>[orig_patent_app_number] => 12033047 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033047
System and method for prioritizing arithmetic instructions Feb 18, 2008 Issued
Array ( [id] => 5393360 [patent_doc_number] => 20090210673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'System and Method for Prioritizing Compare Instructions' [patent_app_type] => utility [patent_app_number] => 12/033122 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8908 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210673.pdf [firstpage_image] =>[orig_patent_app_number] => 12033122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033122
System and method for prioritizing compare instructions Feb 18, 2008 Issued
Array ( [id] => 5393364 [patent_doc_number] => 20090210677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline' [patent_app_type] => utility [patent_app_number] => 12/033140 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210677.pdf [firstpage_image] =>[orig_patent_app_number] => 12033140 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033140
System and Method for Optimization Within a Group Priority Issue Schema for a Cascaded Pipeline Feb 18, 2008 Abandoned
Array ( [id] => 5393359 [patent_doc_number] => 20090210672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'System and Method for Resolving Issue Conflicts of Load Instructions' [patent_app_type] => utility [patent_app_number] => 12/033111 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210672.pdf [firstpage_image] =>[orig_patent_app_number] => 12033111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/033111
System and Method for Resolving Issue Conflicts of Load Instructions Feb 18, 2008 Abandoned
Array ( [id] => 4747265 [patent_doc_number] => 20080091867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Shared interrupt controller for a multi-threaded processor' [patent_app_type] => utility [patent_app_number] => 11/954615 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6459 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091867.pdf [firstpage_image] =>[orig_patent_app_number] => 11954615 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954615
Shared interrupt controller for a multi-threaded processor Dec 11, 2007 Issued
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