Search

Jeffery Shawn Zweizig

Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2849, 2816, 2842, 2504
Total Applications
2645
Issued Applications
2451
Pending Applications
87
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4458149 [patent_doc_number] => 07893754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-22 [patent_title] => 'Temperature independent reference circuit' [patent_app_type] => utility [patent_app_number] => 12/587204 [patent_app_country] => US [patent_app_date] => 2009-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2496 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893754.pdf [firstpage_image] =>[orig_patent_app_number] => 12587204 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/587204
Temperature independent reference circuit Oct 1, 2009 Issued
Array ( [id] => 4434237 [patent_doc_number] => 07969239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Charge pump circuit and a novel capacitor for a memory integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/569832 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5674 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969239.pdf [firstpage_image] =>[orig_patent_app_number] => 12569832 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/569832
Charge pump circuit and a novel capacitor for a memory integrated circuit Sep 28, 2009 Issued
Array ( [id] => 6522467 [patent_doc_number] => 20100123517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'GATE-CONTROLLED RECTIFIER AND APPLICATION TO RECTIFICATION CIRCUITS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/569298 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3454 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123517.pdf [firstpage_image] =>[orig_patent_app_number] => 12569298 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/569298
Gate-controlled rectifier and application to rectification circuits thereof Sep 28, 2009 Issued
Array ( [id] => 4601170 [patent_doc_number] => 07978006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Quantum interference transistors and methods of manufacturing and operating the same' [patent_app_type] => utility [patent_app_number] => 12/585724 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978006.pdf [firstpage_image] =>[orig_patent_app_number] => 12585724 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585724
Quantum interference transistors and methods of manufacturing and operating the same Sep 22, 2009 Issued
Array ( [id] => 6524738 [patent_doc_number] => 20100231289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'CMOS BIAS CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/563575 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20100231289.pdf [firstpage_image] =>[orig_patent_app_number] => 12563575 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563575
CMOS bias circuit Sep 20, 2009 Issued
Array ( [id] => 4500977 [patent_doc_number] => 07948307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Dual dielectric tri-gate field effect transistor' [patent_app_type] => utility [patent_app_number] => 12/561880 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3222 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948307.pdf [firstpage_image] =>[orig_patent_app_number] => 12561880 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561880
Dual dielectric tri-gate field effect transistor Sep 16, 2009 Issued
Array ( [id] => 4446426 [patent_doc_number] => 07863966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-04 [patent_title] => 'Readout circuit for touch panel' [patent_app_type] => utility [patent_app_number] => 12/561857 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3752 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863966.pdf [firstpage_image] =>[orig_patent_app_number] => 12561857 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561857
Readout circuit for touch panel Sep 16, 2009 Issued
Array ( [id] => 4489967 [patent_doc_number] => 07884664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Input device, and multi-function peripheral' [patent_app_type] => utility [patent_app_number] => 12/550194 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 10562 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884664.pdf [firstpage_image] =>[orig_patent_app_number] => 12550194 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550194
Input device, and multi-function peripheral Aug 27, 2009 Issued
Array ( [id] => 4480360 [patent_doc_number] => 07906996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-15 [patent_title] => 'System and method for controlling an integrated circuit in different operational modes' [patent_app_type] => utility [patent_app_number] => 12/543467 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/906/07906996.pdf [firstpage_image] =>[orig_patent_app_number] => 12543467 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543467
System and method for controlling an integrated circuit in different operational modes Aug 17, 2009 Issued
Array ( [id] => 4434224 [patent_doc_number] => 07969231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Internal voltage generating circuit' [patent_app_type] => utility [patent_app_number] => 12/497090 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5697 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969231.pdf [firstpage_image] =>[orig_patent_app_number] => 12497090 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497090
Internal voltage generating circuit Jul 1, 2009 Issued
Array ( [id] => 6287360 [patent_doc_number] => 20100237930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'INTERNAL VOLTAGE GENERATING APPARATUS AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/494437 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6172 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237930.pdf [firstpage_image] =>[orig_patent_app_number] => 12494437 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494437
Internal voltage generating apparatus and method for controlling the same Jun 29, 2009 Issued
Array ( [id] => 5395536 [patent_doc_number] => 20090315599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'CIRCUIT WITH A REGULATED CHARGE PUMP' [patent_app_type] => utility [patent_app_number] => 12/490062 [patent_app_country] => US [patent_app_date] => 2009-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3218 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315599.pdf [firstpage_image] =>[orig_patent_app_number] => 12490062 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/490062
Circuit with a regulated charge pump Jun 22, 2009 Issued
Array ( [id] => 6576628 [patent_doc_number] => 20100321100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'NEGATIVE ANALOG SWITCH DESIGN' [patent_app_type] => utility [patent_app_number] => 12/488287 [patent_app_country] => US [patent_app_date] => 2009-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3900 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20100321100.pdf [firstpage_image] =>[orig_patent_app_number] => 12488287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/488287
Negative analog switch design Jun 18, 2009 Issued
Array ( [id] => 5462196 [patent_doc_number] => 20090322396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'CIRCUIT TO REDUCE DUTY CYCLE DISTORTION' [patent_app_type] => utility [patent_app_number] => 12/486579 [patent_app_country] => US [patent_app_date] => 2009-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6961 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0322/20090322396.pdf [firstpage_image] =>[orig_patent_app_number] => 12486579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/486579
Circuit to reduce duty cycle distortion Jun 16, 2009 Issued
Array ( [id] => 83261 [patent_doc_number] => 07746149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Voltage level shift circuit and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/484664 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6232 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746149.pdf [firstpage_image] =>[orig_patent_app_number] => 12484664 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484664
Voltage level shift circuit and semiconductor integrated circuit Jun 14, 2009 Issued
Array ( [id] => 6591457 [patent_doc_number] => 20100308900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'METHOD AND CIRCUIT FOR CHARGING AND DISCHARGING A CIRCUIT NODE' [patent_app_type] => utility [patent_app_number] => 12/479940 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0308/20100308900.pdf [firstpage_image] =>[orig_patent_app_number] => 12479940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479940
Method and circuit for charging and discharging a circuit node Jun 7, 2009 Issued
Array ( [id] => 4537758 [patent_doc_number] => 07872520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/475867 [patent_app_country] => US [patent_app_date] => 2009-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6046 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/872/07872520.pdf [firstpage_image] =>[orig_patent_app_number] => 12475867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/475867
Semiconductor integrated circuit device May 31, 2009 Issued
Array ( [id] => 4504520 [patent_doc_number] => 07920016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Monolithic voltage reference device with internal, multi-temperature drift data and related testing procedures' [patent_app_type] => utility [patent_app_number] => 12/475184 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4910 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/920/07920016.pdf [firstpage_image] =>[orig_patent_app_number] => 12475184 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/475184
Monolithic voltage reference device with internal, multi-temperature drift data and related testing procedures May 28, 2009 Issued
Array ( [id] => 4446425 [patent_doc_number] => 07863965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Temperature sensor circuit and method for controlling the same' [patent_app_type] => utility [patent_app_number] => 12/454256 [patent_app_country] => US [patent_app_date] => 2009-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2791 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863965.pdf [firstpage_image] =>[orig_patent_app_number] => 12454256 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/454256
Temperature sensor circuit and method for controlling the same May 12, 2009 Issued
Array ( [id] => 5316162 [patent_doc_number] => 20090280760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'RADIO COMMUNICATION APPARATUS AND RADIO COMMUNICATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/431894 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20090280760.pdf [firstpage_image] =>[orig_patent_app_number] => 12431894 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/431894
Radio communication apparatus and radio communication method Apr 28, 2009 Issued
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