Jeffery Shawn Zweizig

Array ( [id] => 4776496 [patent_doc_number] => 20080284494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'FUSE DEVICE, METHOD FOR WRITING DATA, METHOD FOR READING DATA, AND METHOD FOR WRITING AND READING DATA' [patent_app_type] => utility [patent_app_number] => 12/118033 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5526 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20080284494.pdf [firstpage_image] =>[orig_patent_app_number] => 12118033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5328439 [patent_doc_number] => 20090108916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'PUMP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/117691 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3695 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108916.pdf [firstpage_image] =>[orig_patent_app_number] => 12117691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4614760 [patent_doc_number] => 07990204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Voltage generator that prevents latch-up' [patent_app_type] => utility [patent_app_number] => 12/117445 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7297 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990204.pdf [firstpage_image] =>[orig_patent_app_number] => 12117445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5395551 [patent_doc_number] => 20090315614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'DIVERSITY SIGNAL PROCESSING SYSTEM AND A PRODUCING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/109091 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3562 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315614.pdf [firstpage_image] =>[orig_patent_app_number] => 12109091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4572774 [patent_doc_number] => 07847619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-07 [patent_title] => 'Servo loop for well bias voltage source' [patent_app_type] => utility [patent_app_number] => 12/107733 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2857 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/847/07847619.pdf [firstpage_image] =>[orig_patent_app_number] => 12107733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 240138 [patent_doc_number] => 07592858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-22 [patent_title] => 'Circuit and method for a gate control circuit with reduced voltage stress' [patent_app_type] => utility [patent_app_number] => 12/103332 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7663 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592858.pdf [firstpage_image] =>[orig_patent_app_number] => 12103332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 152878 [patent_doc_number] => 07683689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Delay circuit with delay cells in different orientations' [patent_app_type] => utility [patent_app_number] => 12/082296 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6779 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683689.pdf [firstpage_image] =>[orig_patent_app_number] => 12082296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 221559 [patent_doc_number] => 07609105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Voltage level generating device' [patent_app_type] => utility [patent_app_number] => 12/099767 [patent_app_country] => US [patent_app_date] => 2008-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3926 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/609/07609105.pdf [firstpage_image] =>[orig_patent_app_number] => 12099767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4434234 [patent_doc_number] => 07969238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Active filter having a multilevel topology' [patent_app_type] => utility [patent_app_number] => 12/595283 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2513 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969238.pdf [firstpage_image] =>[orig_patent_app_number] => 12595283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 203712 [patent_doc_number] => 07633325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Signal generation apparatus for frequency conversion in communication system' [patent_app_type] => utility [patent_app_number] => 12/075320 [patent_app_country] => US [patent_app_date] => 2008-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/633/07633325.pdf [firstpage_image] =>[orig_patent_app_number] => 12075320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6305708 [patent_doc_number] => 20100109614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'SIGNAL PROCESSOR COMPRISING A REFERENCE VOLTAGE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/529763 [patent_app_country] => US [patent_app_date] => 2008-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8226 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109614.pdf [firstpage_image] =>[orig_patent_app_number] => 12529763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7599314 [patent_doc_number] => 07583134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Semiconductor integrated circuit and method of controlling internal voltage of the same' [patent_app_type] => utility [patent_app_number] => 12/073115 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4833 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/583/07583134.pdf [firstpage_image] =>[orig_patent_app_number] => 12073115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4696066 [patent_doc_number] => 20080218250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'CHARGE PUMP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/038579 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6931 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20080218250.pdf [firstpage_image] =>[orig_patent_app_number] => 12038579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 282386 [patent_doc_number] => 07554387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'Precision on chip bias current generation' [patent_app_type] => utility [patent_app_number] => 12/038125 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554387.pdf [firstpage_image] =>[orig_patent_app_number] => 12038125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 236703 [patent_doc_number] => 07595685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-29 [patent_title] => 'Power efficient and fast settling bias current generation circuit and system' [patent_app_type] => utility [patent_app_number] => 12/038186 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595685.pdf [firstpage_image] =>[orig_patent_app_number] => 12038186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5439727 [patent_doc_number] => 20090091366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'VOLTAGE GENERATOR OF SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/034529 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2916 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091366.pdf [firstpage_image] =>[orig_patent_app_number] => 12034529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5499857 [patent_doc_number] => 20090160545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'DUAL VOLTAGE SWITCHING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/033873 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1539 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20090160545.pdf [firstpage_image] =>[orig_patent_app_number] => 12033873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 274812 [patent_doc_number] => 07560979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-14 [patent_title] => 'Reference voltage devices and methods thereof' [patent_app_type] => utility [patent_app_number] => 12/032717 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3563 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560979.pdf [firstpage_image] =>[orig_patent_app_number] => 12032717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5389607 [patent_doc_number] => 20090206919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'NO-TRIM LOW-DROPOUT (LDO) AND SWITCH-MODE VOLTAGE REGULATOR CIRCUIT AND TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 12/032565 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2952 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20090206919.pdf [firstpage_image] =>[orig_patent_app_number] => 12032565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4871181 [patent_doc_number] => 20080197915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'SEMICONDUCTOR DEVICE CHIP, SEMICONDUCTOR DEVICE SYSTEM, AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/032326 [patent_app_country] => US [patent_app_date] => 2008-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197915.pdf [firstpage_image] =>[orig_patent_app_number] => 12032326 [rel_patent_id] =>[rel_patent_doc_number] =>)