
Jeffery Shawn Zweizig
Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2816, 2849, 2842, 2504 |
| Total Applications | 2640 |
| Issued Applications | 2460 |
| Pending Applications | 67 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 174395
[patent_doc_number] => 07659775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-09
[patent_title] => 'Output differential stage'
[patent_app_type] => utility
[patent_app_number] => 11/861364
[patent_app_country] => US
[patent_app_date] => 2007-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2060
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/659/07659775.pdf
[firstpage_image] =>[orig_patent_app_number] => 11861364
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/861364 | Output differential stage | Sep 25, 2007 | Issued |
Array
(
[id] => 4795737
[patent_doc_number] => 20080007323
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'Systems and methods forminimizing static leakage of an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/900971
[patent_app_country] => US
[patent_app_date] => 2007-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9091
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20080007323.pdf
[firstpage_image] =>[orig_patent_app_number] => 11900971
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/900971 | Systems and methods for minimizing static leakage of an integrated circuit | Sep 13, 2007 | Issued |
Array
(
[id] => 4795739
[patent_doc_number] => 20080007325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'Current source circuit'
[patent_app_type] => utility
[patent_app_number] => 11/896198
[patent_app_country] => US
[patent_app_date] => 2007-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4931
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20080007325.pdf
[firstpage_image] =>[orig_patent_app_number] => 11896198
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/896198 | Current source circuit | Aug 29, 2007 | Issued |
Array
(
[id] => 6312979
[patent_doc_number] => 20100194466
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-05
[patent_title] => 'QUANTUM BIT VARIABLE COUPLING METHOD, QUANTUM COMPUTING CIRCUIT USING THE METHOD, AND VARIABLE COUPLER'
[patent_app_type] => utility
[patent_app_number] => 12/439970
[patent_app_country] => US
[patent_app_date] => 2007-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6745
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20100194466.pdf
[firstpage_image] =>[orig_patent_app_number] => 12439970
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/439970 | Quantum bit variable coupling method, quantum computing circuit using the method, and variable coupler | Aug 28, 2007 | Issued |
Array
(
[id] => 229419
[patent_doc_number] => 07602234
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-13
[patent_title] => 'Substantially zero temperature coefficient bias generator'
[patent_app_type] => utility
[patent_app_number] => 11/782478
[patent_app_country] => US
[patent_app_date] => 2007-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7079
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/602/07602234.pdf
[firstpage_image] =>[orig_patent_app_number] => 11782478
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/782478 | Substantially zero temperature coefficient bias generator | Jul 23, 2007 | Issued |
Array
(
[id] => 212055
[patent_doc_number] => 07622962
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-24
[patent_title] => 'Sense amplifier control signal generating circuit of semiconductor memory apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/826924
[patent_app_country] => US
[patent_app_date] => 2007-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2336
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/622/07622962.pdf
[firstpage_image] =>[orig_patent_app_number] => 11826924
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/826924 | Sense amplifier control signal generating circuit of semiconductor memory apparatus | Jul 18, 2007 | Issued |
Array
(
[id] => 186306
[patent_doc_number] => 07646226
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-12
[patent_title] => 'Adaptive bandwidth phase locked loops with current boosting circuits'
[patent_app_type] => utility
[patent_app_number] => 11/826901
[patent_app_country] => US
[patent_app_date] => 2007-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 4678
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/646/07646226.pdf
[firstpage_image] =>[orig_patent_app_number] => 11826901
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/826901 | Adaptive bandwidth phase locked loops with current boosting circuits | Jul 18, 2007 | Issued |
Array
(
[id] => 4877235
[patent_doc_number] => 20080150618
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'Apparatus and method for generating internal voltage in semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/826913
[patent_app_country] => US
[patent_app_date] => 2007-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2983
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0150/20080150618.pdf
[firstpage_image] =>[orig_patent_app_number] => 11826913
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/826913 | Apparatus and method for generating internal voltage in semiconductor integrated circuit | Jul 18, 2007 | Issued |
Array
(
[id] => 289484
[patent_doc_number] => 07548101
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-16
[patent_title] => 'Delay locked loop circuit for semiconductor memory apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/826916
[patent_app_country] => US
[patent_app_date] => 2007-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 5001
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/548/07548101.pdf
[firstpage_image] =>[orig_patent_app_number] => 11826916
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/826916 | Delay locked loop circuit for semiconductor memory apparatus | Jul 18, 2007 | Issued |
Array
(
[id] => 256913
[patent_doc_number] => 07576591
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Charge pump system and corresponding method for managing voltage generation'
[patent_app_type] => utility
[patent_app_number] => 11/780206
[patent_app_country] => US
[patent_app_date] => 2007-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5067
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/576/07576591.pdf
[firstpage_image] =>[orig_patent_app_number] => 11780206
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/780206 | Charge pump system and corresponding method for managing voltage generation | Jul 18, 2007 | Issued |
Array
(
[id] => 4801043
[patent_doc_number] => 20080012630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-17
[patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING CURRENT MIRROR CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/773996
[patent_app_country] => US
[patent_app_date] => 2007-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3278
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20080012630.pdf
[firstpage_image] =>[orig_patent_app_number] => 11773996
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/773996 | Semiconductor device including current mirror circuit | Jul 5, 2007 | Issued |
Array
(
[id] => 7595022
[patent_doc_number] => 07626440
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-12-01
[patent_title] => 'High speed level shift'
[patent_app_type] => utility
[patent_app_number] => 11/825164
[patent_app_country] => US
[patent_app_date] => 2007-07-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5217
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/626/07626440.pdf
[firstpage_image] =>[orig_patent_app_number] => 11825164
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/825164 | High speed level shift | Jul 3, 2007 | Issued |
Array
(
[id] => 174389
[patent_doc_number] => 07659769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-09
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/771779
[patent_app_country] => US
[patent_app_date] => 2007-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 27
[patent_no_of_words] => 10825
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/659/07659769.pdf
[firstpage_image] =>[orig_patent_app_number] => 11771779
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/771779 | Semiconductor device | Jun 28, 2007 | Issued |
Array
(
[id] => 590707
[patent_doc_number] => 07443226
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-10-28
[patent_title] => 'Emitter area trim scheme for a PTAT current source'
[patent_app_type] => utility
[patent_app_number] => 11/766657
[patent_app_country] => US
[patent_app_date] => 2007-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 10666
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 337
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/443/07443226.pdf
[firstpage_image] =>[orig_patent_app_number] => 11766657
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/766657 | Emitter area trim scheme for a PTAT current source | Jun 20, 2007 | Issued |
Array
(
[id] => 5245577
[patent_doc_number] => 20070241811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-18
[patent_title] => 'Methods and Systems for Reducing Leakage Current in Semiconductor Circuits'
[patent_app_type] => utility
[patent_app_number] => 11/765273
[patent_app_country] => US
[patent_app_date] => 2007-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9428
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0241/20070241811.pdf
[firstpage_image] =>[orig_patent_app_number] => 11765273
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/765273 | Methods and systems for reducing leakage current in semiconductor circuits | Jun 18, 2007 | Issued |
Array
(
[id] => 5506286
[patent_doc_number] => 20090079493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-26
[patent_title] => 'Temperature-Compensated Current Generator, for Instance for 1-10V Interfaces'
[patent_app_type] => utility
[patent_app_number] => 12/226501
[patent_app_country] => US
[patent_app_date] => 2007-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1533
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20090079493.pdf
[firstpage_image] =>[orig_patent_app_number] => 12226501
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/226501 | Temperature-compensated current generator, for instance for 1-10V interfaces | Jun 3, 2007 | Issued |
Array
(
[id] => 4743788
[patent_doc_number] => 20080088389
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'Charge Domain Filter Device'
[patent_app_type] => utility
[patent_app_number] => 11/754763
[patent_app_country] => US
[patent_app_date] => 2007-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8867
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20080088389.pdf
[firstpage_image] =>[orig_patent_app_number] => 11754763
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754763 | Charge domain filter device | May 28, 2007 | Issued |
Array
(
[id] => 589292
[patent_doc_number] => 07446596
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-11-04
[patent_title] => 'Low voltage charge pump'
[patent_app_type] => utility
[patent_app_number] => 11/753932
[patent_app_country] => US
[patent_app_date] => 2007-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3601
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/446/07446596.pdf
[firstpage_image] =>[orig_patent_app_number] => 11753932
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/753932 | Low voltage charge pump | May 24, 2007 | Issued |
Array
(
[id] => 4789934
[patent_doc_number] => 20080290907
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'THRESHOLD CONTROL CIRCUITRY FOR MULTIPLE CURRENT SIGNAL RECEIVERS'
[patent_app_type] => utility
[patent_app_number] => 11/753266
[patent_app_country] => US
[patent_app_date] => 2007-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2534
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20080290907.pdf
[firstpage_image] =>[orig_patent_app_number] => 11753266
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/753266 | Threshold control circuitry for multiple current signal receivers | May 23, 2007 | Issued |
Array
(
[id] => 4913531
[patent_doc_number] => 20080094130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'SUPPLY-INDEPENDENT BIASING CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/751379
[patent_app_country] => US
[patent_app_date] => 2007-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5351
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20080094130.pdf
[firstpage_image] =>[orig_patent_app_number] => 11751379
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/751379 | SUPPLY-INDEPENDENT BIASING CIRCUIT | May 20, 2007 | Abandoned |