Jeffery Shawn Zweizig

Array ( [id] => 5060335 [patent_doc_number] => 20070221972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'MOSFET for synchronous rectification' [patent_app_type] => utility [patent_app_number] => 11/804877 [patent_app_country] => US [patent_app_date] => 2007-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3913 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20070221972.pdf [firstpage_image] =>[orig_patent_app_number] => 11804877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 356742 [patent_doc_number] => 07489182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Charge pump start up circuit and method thereof' [patent_app_type] => utility [patent_app_number] => 11/749872 [patent_app_country] => US [patent_app_date] => 2007-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1982 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489182.pdf [firstpage_image] =>[orig_patent_app_number] => 11749872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 592792 [patent_doc_number] => 07439794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Power source circuit' [patent_app_type] => utility [patent_app_number] => 11/748132 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6143 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/439/07439794.pdf [firstpage_image] =>[orig_patent_app_number] => 11748132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 349384 [patent_doc_number] => 07495503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Current biasing circuit' [patent_app_type] => utility [patent_app_number] => 11/747917 [patent_app_country] => US [patent_app_date] => 2007-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2454 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495503.pdf [firstpage_image] =>[orig_patent_app_number] => 11747917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5026614 [patent_doc_number] => 20070268060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'METHOD AND CIRCUIT ARRANGEMENT FOR GENERATING A PERIODIC ELECTRIC SIGNAL WITH CONTROLLABLE PHASE' [patent_app_type] => utility [patent_app_number] => 11/745790 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3764 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20070268060.pdf [firstpage_image] =>[orig_patent_app_number] => 11745790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4544572 [patent_doc_number] => 07876146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Method and apparatus for powering down analog integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/745778 [patent_app_country] => US [patent_app_date] => 2007-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6897 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/876/07876146.pdf [firstpage_image] =>[orig_patent_app_number] => 11745778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5129415 [patent_doc_number] => 20070205812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Current drive circuit reducing VDS dependency' [patent_app_type] => utility [patent_app_number] => 11/800323 [patent_app_country] => US [patent_app_date] => 2007-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3143 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20070205812.pdf [firstpage_image] =>[orig_patent_app_number] => 11800323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 300399 [patent_doc_number] => 07538603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Signal distribution architecture and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/744694 [patent_app_country] => US [patent_app_date] => 2007-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 7138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538603.pdf [firstpage_image] =>[orig_patent_app_number] => 11744694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 205622 [patent_doc_number] => 07629832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-08 [patent_title] => 'Current source circuit and design methodology' [patent_app_type] => utility [patent_app_number] => 11/742405 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3453 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/629/07629832.pdf [firstpage_image] =>[orig_patent_app_number] => 11742405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4528433 [patent_doc_number] => 07952398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Bias circuit for common-mode and semiconductor process voltage and temperature optimization for a receiver assembly' [patent_app_type] => utility [patent_app_number] => 11/741115 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952398.pdf [firstpage_image] =>[orig_patent_app_number] => 11741115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4702501 [patent_doc_number] => 20080062023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'LOW-PASS FILTER AND VOLTAGE-CURRENT CONVERSION CIRCUIT USED IN THE SAME' [patent_app_type] => utility [patent_app_number] => 11/739826 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1837 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20080062023.pdf [firstpage_image] =>[orig_patent_app_number] => 11739826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7492942 [patent_doc_number] => 08030990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Measuring instrument in two-conductor technology' [patent_app_type] => utility [patent_app_number] => 12/298284 [patent_app_country] => US [patent_app_date] => 2007-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3598 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030990.pdf [firstpage_image] =>[orig_patent_app_number] => 12298284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4655338 [patent_doc_number] => 20080024199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Step-up booster circuit' [patent_app_type] => utility [patent_app_number] => 11/785308 [patent_app_country] => US [patent_app_date] => 2007-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8074 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20080024199.pdf [firstpage_image] =>[orig_patent_app_number] => 11785308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 323201 [patent_doc_number] => 07518435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Precharged power-down biasing circuit' [patent_app_type] => utility [patent_app_number] => 11/785216 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2545 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518435.pdf [firstpage_image] =>[orig_patent_app_number] => 11785216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 278561 [patent_doc_number] => 07557639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Semiconductor device employing standby current reduction' [patent_app_type] => utility [patent_app_number] => 11/735843 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7300 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/557/07557639.pdf [firstpage_image] =>[orig_patent_app_number] => 11735843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4680294 [patent_doc_number] => 20080246520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'DELAY-LOCKED LOOP (DLL) SYSTEM FOR DETERMINING FORWARD CLOCK PATH DELAY' [patent_app_type] => utility [patent_app_number] => 11/697858 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6273 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20080246520.pdf [firstpage_image] =>[orig_patent_app_number] => 11697858 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5124006 [patent_doc_number] => 20070236277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Semiconductor integrated circuit device and substrate bias controlling method' [patent_app_type] => utility [patent_app_number] => 11/783432 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8819 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20070236277.pdf [firstpage_image] =>[orig_patent_app_number] => 11783432 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5089513 [patent_doc_number] => 20070229152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'FILTER ADJUSTMENT CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/695204 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9513 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20070229152.pdf [firstpage_image] =>[orig_patent_app_number] => 11695204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4715987 [patent_doc_number] => 20080238509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'BOUNDING A DUTY CYCLE USING A C-ELEMENT' [patent_app_type] => utility [patent_app_number] => 11/694440 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20080238509.pdf [firstpage_image] =>[orig_patent_app_number] => 11694440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4716012 [patent_doc_number] => 20080238534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'PHASE SHIFTING IN DLL/PLL' [patent_app_type] => utility [patent_app_number] => 11/691849 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11251 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20080238534.pdf [firstpage_image] =>[orig_patent_app_number] => 11691849 [rel_patent_id] =>[rel_patent_doc_number] =>)