Search

Jeffery Shawn Zweizig

Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2849, 2842, 2504
Total Applications
2640
Issued Applications
2460
Pending Applications
67
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4737683 [patent_doc_number] => 20080231335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'CIRCUIT TO REDUCE DUTY CYCLE DISTORTION' [patent_app_type] => utility [patent_app_number] => 11/688649 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3368 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20080231335.pdf [firstpage_image] =>[orig_patent_app_number] => 11688649 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688649
CIRCUIT TO REDUCE DUTY CYCLE DISTORTION Mar 19, 2007 Abandoned
Array ( [id] => 289483 [patent_doc_number] => 07548100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Delay locked loop' [patent_app_type] => utility [patent_app_number] => 11/687396 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2595 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/548/07548100.pdf [firstpage_image] =>[orig_patent_app_number] => 11687396 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/687396
Delay locked loop Mar 15, 2007 Issued
Array ( [id] => 594384 [patent_doc_number] => 07436241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Charge pump' [patent_app_type] => utility [patent_app_number] => 11/685162 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5661 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 499 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/436/07436241.pdf [firstpage_image] =>[orig_patent_app_number] => 11685162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685162
Charge pump Mar 11, 2007 Issued
Array ( [id] => 565991 [patent_doc_number] => 07471133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-30 [patent_title] => 'Modulator circuit with linear and non-linear control' [patent_app_type] => utility [patent_app_number] => 11/683215 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5559 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/471/07471133.pdf [firstpage_image] =>[orig_patent_app_number] => 11683215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683215
Modulator circuit with linear and non-linear control Mar 6, 2007 Issued
Array ( [id] => 594426 [patent_doc_number] => 07436246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Pin number reduction circuit and methodology for mixed-signal IC, memory IC, and SOC' [patent_app_type] => utility [patent_app_number] => 11/711399 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/436/07436246.pdf [firstpage_image] =>[orig_patent_app_number] => 11711399 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711399
Pin number reduction circuit and methodology for mixed-signal IC, memory IC, and SOC Feb 25, 2007 Issued
Array ( [id] => 5164423 [patent_doc_number] => 20070286007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'High-voltage generating circuit including charge transfer switching circuit for selectively controlling body bias voltage of charge transfer device' [patent_app_type] => utility [patent_app_number] => 11/709768 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4503 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20070286007.pdf [firstpage_image] =>[orig_patent_app_number] => 11709768 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709768
High-voltage generating circuit including charge transfer switching circuit for selectively controlling body bias voltage of charge transfer device Feb 22, 2007 Issued
Array ( [id] => 798301 [patent_doc_number] => 07427891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Charge pump-type booster circuit' [patent_app_type] => utility [patent_app_number] => 11/709915 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3957 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/427/07427891.pdf [firstpage_image] =>[orig_patent_app_number] => 11709915 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709915
Charge pump-type booster circuit Feb 21, 2007 Issued
Array ( [id] => 5257223 [patent_doc_number] => 20070210855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Replica biased low power voltage regulator' [patent_app_type] => utility [patent_app_number] => 11/709990 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210855.pdf [firstpage_image] =>[orig_patent_app_number] => 11709990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709990
Replica biased system Feb 21, 2007 Issued
Array ( [id] => 5003045 [patent_doc_number] => 20070200612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Power supply apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/708353 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3978 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20070200612.pdf [firstpage_image] =>[orig_patent_app_number] => 11708353 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708353
Power supply apparatus and method Feb 20, 2007 Issued
Array ( [id] => 5110910 [patent_doc_number] => 20070194825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Adaptive delay-locked loops and methods of generating clock signals using the same' [patent_app_type] => utility [patent_app_number] => 11/708432 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8303 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194825.pdf [firstpage_image] =>[orig_patent_app_number] => 11708432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708432
Adaptive delay-locked loops and methods of generating clock signals using the same Feb 20, 2007 Issued
Array ( [id] => 5060861 [patent_doc_number] => 20070222500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 11/707001 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20070222500.pdf [firstpage_image] =>[orig_patent_app_number] => 11707001 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707001
Boosting voltage generating circuit for generating a stable boosting voltage under a wider range of supply voltage and semiconductor memory device having the same Feb 15, 2007 Issued
Array ( [id] => 5257224 [patent_doc_number] => 20070210856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Band gap constant-voltage circuit' [patent_app_type] => utility [patent_app_number] => 11/706479 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2720 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210856.pdf [firstpage_image] =>[orig_patent_app_number] => 11706479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706479
Band gap constant-voltage circuit Feb 14, 2007 Issued
Array ( [id] => 4871180 [patent_doc_number] => 20080197914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Dynamic leakage control using selective back-biasing' [patent_app_type] => utility [patent_app_number] => 11/707602 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5762 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197914.pdf [firstpage_image] =>[orig_patent_app_number] => 11707602 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707602
Dynamic leakage control using selective back-biasing Feb 14, 2007 Abandoned
Array ( [id] => 5110923 [patent_doc_number] => 20070194838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Current mirror with improved output impedance at low power supplies' [patent_app_type] => utility [patent_app_number] => 11/706487 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2557 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194838.pdf [firstpage_image] =>[orig_patent_app_number] => 11706487 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706487
Current mirror with improved output impedance at low power supplies Feb 14, 2007 Abandoned
Array ( [id] => 6419985 [patent_doc_number] => 20100277233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'Gallium nitride traveling wave structures' [patent_app_type] => utility [patent_app_number] => 11/705344 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20100277233.pdf [firstpage_image] =>[orig_patent_app_number] => 11705344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705344
Gallium nitride traveling wave structures Feb 11, 2007 Issued
Array ( [id] => 4649258 [patent_doc_number] => 20080036513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'PLL circuit' [patent_app_type] => utility [patent_app_number] => 11/700860 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6813 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036513.pdf [firstpage_image] =>[orig_patent_app_number] => 11700860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/700860
PLL circuit Jan 31, 2007 Issued
Array ( [id] => 5257220 [patent_doc_number] => 20070210852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Voltage level shift circuit and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/699130 [patent_app_country] => US [patent_app_date] => 2007-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6210 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210852.pdf [firstpage_image] =>[orig_patent_app_number] => 11699130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/699130
Voltage level shift circuit and semiconductor integrated circuit Jan 25, 2007 Issued
Array ( [id] => 886490 [patent_doc_number] => 07352234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Current control technique' [patent_app_type] => utility [patent_app_number] => 11/625711 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6512 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352234.pdf [firstpage_image] =>[orig_patent_app_number] => 11625711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625711
Current control technique Jan 21, 2007 Issued
Array ( [id] => 267592 [patent_doc_number] => 07567119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Current limiting protection circuit' [patent_app_type] => utility [patent_app_number] => 11/621595 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2909 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/567/07567119.pdf [firstpage_image] =>[orig_patent_app_number] => 11621595 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/621595
Current limiting protection circuit Jan 9, 2007 Issued
Array ( [id] => 5158545 [patent_doc_number] => 20070171589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Zapping Circuit' [patent_app_type] => utility [patent_app_number] => 11/620250 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3843 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20070171589.pdf [firstpage_image] =>[orig_patent_app_number] => 11620250 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620250
Zapping Circuit Jan 4, 2007 Abandoned
Menu