Search

Jeffery Shawn Zweizig

Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2849, 2842, 2504
Total Applications
2640
Issued Applications
2460
Pending Applications
67
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5003055 [patent_doc_number] => 20070200622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'MODULATOR APPARATUS OPERATING AT LOW SUPPLY VOLTAGE, AND CORRESPONDING METHOD OF MODULATION' [patent_app_type] => utility [patent_app_number] => 11/619750 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3841 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20070200622.pdf [firstpage_image] =>[orig_patent_app_number] => 11619750 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619750
Modulator apparatus operating at low supply voltage, and corresponding method of modulation Jan 3, 2007 Issued
Array ( [id] => 353188 [patent_doc_number] => 07492214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Analog voltage generator with self-biased capacitive feedback stage' [patent_app_type] => utility [patent_app_number] => 11/618918 [patent_app_country] => US [patent_app_date] => 2007-01-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/492/07492214.pdf [firstpage_image] =>[orig_patent_app_number] => 11618918 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618918
Analog voltage generator with self-biased capacitive feedback stage Dec 31, 2006 Issued
Array ( [id] => 4749783 [patent_doc_number] => 20080157854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'MULTIPLE POLARITY REVERSIBLE CHARGE PUMP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/618841 [patent_app_country] => US [patent_app_date] => 2006-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9029 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157854.pdf [firstpage_image] =>[orig_patent_app_number] => 11618841 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618841
Multiple polarity reversible charge pump circuit Dec 30, 2006 Issued
Array ( [id] => 4749782 [patent_doc_number] => 20080157853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD FOR USING A MULTIPLE POLARITY REVERSIBLE CHARGE PUMP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/618838 [patent_app_country] => US [patent_app_date] => 2006-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8938 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157853.pdf [firstpage_image] =>[orig_patent_app_number] => 11618838 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618838
Method for using a multiple polarity reversible charge pump circuit Dec 30, 2006 Issued
Array ( [id] => 4749781 [patent_doc_number] => 20080157852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'UNIFIED VOLTAGE GENERATION APPARATUS WITH IMPROVED POWER EFFICIENCY' [patent_app_type] => utility [patent_app_number] => 11/618539 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6376 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157852.pdf [firstpage_image] =>[orig_patent_app_number] => 11618539 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618539
Unified voltage generation apparatus with improved power efficiency Dec 28, 2006 Issued
Array ( [id] => 4749658 [patent_doc_number] => 20080157729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'CHARGE PUMP REGULATOR WITH MULTIPLE CONTROL OPTIONS' [patent_app_type] => utility [patent_app_number] => 11/618049 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5068 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157729.pdf [firstpage_image] =>[orig_patent_app_number] => 11618049 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618049
Charge pump regulator with multiple control options Dec 28, 2006 Issued
Array ( [id] => 4902202 [patent_doc_number] => 20080111615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'VOLTAGE GENERATOR IN A FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/617419 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2945 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111615.pdf [firstpage_image] =>[orig_patent_app_number] => 11617419 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/617419
Voltage generator in a flash memory device Dec 27, 2006 Issued
Array ( [id] => 5218436 [patent_doc_number] => 20070159747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 11/615542 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4574 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20070159747.pdf [firstpage_image] =>[orig_patent_app_number] => 11615542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615542
Circuit arrangement and method for operating a circuit arrangement Dec 21, 2006 Issued
Array ( [id] => 573300 [patent_doc_number] => 07466188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Stress control mechanism for use in high-voltage applications in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/614750 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6188 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/466/07466188.pdf [firstpage_image] =>[orig_patent_app_number] => 11614750 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614750
Stress control mechanism for use in high-voltage applications in an integrated circuit Dec 20, 2006 Issued
Array ( [id] => 827391 [patent_doc_number] => 07403062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Dual edge modulated charge pumping circuit and method' [patent_app_type] => utility [patent_app_number] => 11/613181 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4975 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/403/07403062.pdf [firstpage_image] =>[orig_patent_app_number] => 11613181 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613181
Dual edge modulated charge pumping circuit and method Dec 18, 2006 Issued
Array ( [id] => 197921 [patent_doc_number] => 07639066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Circuit and method for suppressing gate induced drain leakage' [patent_app_type] => utility [patent_app_number] => 11/611222 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2807 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639066.pdf [firstpage_image] =>[orig_patent_app_number] => 11611222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611222
Circuit and method for suppressing gate induced drain leakage Dec 14, 2006 Issued
Array ( [id] => 886493 [patent_doc_number] => 07352236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/637714 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13786 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352236.pdf [firstpage_image] =>[orig_patent_app_number] => 11637714 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/637714
Semiconductor integrated circuit device Dec 12, 2006 Issued
Array ( [id] => 163602 [patent_doc_number] => 07671642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Amplitude controlled sawtooth generator' [patent_app_type] => utility [patent_app_number] => 11/610107 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 7473 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/671/07671642.pdf [firstpage_image] =>[orig_patent_app_number] => 11610107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/610107
Amplitude controlled sawtooth generator Dec 12, 2006 Issued
Array ( [id] => 834005 [patent_doc_number] => 07397296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-08 [patent_title] => 'Power supply detection circuit biased by multiple power supply voltages for controlling a signal driver circuit' [patent_app_type] => utility [patent_app_number] => 11/609690 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2967 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397296.pdf [firstpage_image] =>[orig_patent_app_number] => 11609690 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609690
Power supply detection circuit biased by multiple power supply voltages for controlling a signal driver circuit Dec 11, 2006 Issued
Array ( [id] => 4857102 [patent_doc_number] => 20080265952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Gate Driver Circuit for Power Transistor' [patent_app_type] => utility [patent_app_number] => 11/561681 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1097 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265952.pdf [firstpage_image] =>[orig_patent_app_number] => 11561681 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561681
Gate driver circuit for power transistor Nov 19, 2006 Issued
Array ( [id] => 814178 [patent_doc_number] => 07414455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Digital temperature detection circuit for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/599433 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5733 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414455.pdf [firstpage_image] =>[orig_patent_app_number] => 11599433 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/599433
Digital temperature detection circuit for semiconductor device Nov 14, 2006 Issued
Array ( [id] => 4981042 [patent_doc_number] => 20070085599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Potential Detector and Semiconductor Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/558072 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20070085599.pdf [firstpage_image] =>[orig_patent_app_number] => 11558072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/558072
Potential detector and semiconductor integrated circuit Nov 8, 2006 Issued
Array ( [id] => 873817 [patent_doc_number] => 07362165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-22 [patent_title] => 'Servo loop for well bias voltage source' [patent_app_type] => utility [patent_app_number] => 11/591431 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362165.pdf [firstpage_image] =>[orig_patent_app_number] => 11591431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/591431
Servo loop for well bias voltage source Oct 30, 2006 Issued
Array ( [id] => 236685 [patent_doc_number] => 07595667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Drive circuit' [patent_app_type] => utility [patent_app_number] => 11/554158 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3479 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595667.pdf [firstpage_image] =>[orig_patent_app_number] => 11554158 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/554158
Drive circuit Oct 29, 2006 Issued
Array ( [id] => 5042345 [patent_doc_number] => 20070094627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Clock forming method for semiconductor integrated circuit and program product for the method' [patent_app_type] => utility [patent_app_number] => 11/584492 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4034 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094627.pdf [firstpage_image] =>[orig_patent_app_number] => 11584492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584492
Clock forming method for semiconductor integrated circuit and program product for the method Oct 22, 2006 Issued
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