
Jeffery Shawn Zweizig
Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2849, 2816, 2842, 2504 |
| Total Applications | 2645 |
| Issued Applications | 2451 |
| Pending Applications | 87 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4544572
[patent_doc_number] => 07876146
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-25
[patent_title] => 'Method and apparatus for powering down analog integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/745778
[patent_app_country] => US
[patent_app_date] => 2007-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6897
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/876/07876146.pdf
[firstpage_image] =>[orig_patent_app_number] => 11745778
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/745778 | Method and apparatus for powering down analog integrated circuits | May 7, 2007 | Issued |
Array
(
[id] => 300399
[patent_doc_number] => 07538603
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-26
[patent_title] => 'Signal distribution architecture and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/744694
[patent_app_country] => US
[patent_app_date] => 2007-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 28
[patent_no_of_words] => 7138
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/538/07538603.pdf
[firstpage_image] =>[orig_patent_app_number] => 11744694
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/744694 | Signal distribution architecture and semiconductor device | May 3, 2007 | Issued |
Array
(
[id] => 5129415
[patent_doc_number] => 20070205812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-06
[patent_title] => 'Current drive circuit reducing VDS dependency'
[patent_app_type] => utility
[patent_app_number] => 11/800323
[patent_app_country] => US
[patent_app_date] => 2007-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3143
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20070205812.pdf
[firstpage_image] =>[orig_patent_app_number] => 11800323
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/800323 | Current drive circuit reducing VDS dependency | May 3, 2007 | Issued |
Array
(
[id] => 205622
[patent_doc_number] => 07629832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-12-08
[patent_title] => 'Current source circuit and design methodology'
[patent_app_type] => utility
[patent_app_number] => 11/742405
[patent_app_country] => US
[patent_app_date] => 2007-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3453
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/629/07629832.pdf
[firstpage_image] =>[orig_patent_app_number] => 11742405
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/742405 | Current source circuit and design methodology | Apr 29, 2007 | Issued |
Array
(
[id] => 4528433
[patent_doc_number] => 07952398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'Bias circuit for common-mode and semiconductor process voltage and temperature optimization for a receiver assembly'
[patent_app_type] => utility
[patent_app_number] => 11/741115
[patent_app_country] => US
[patent_app_date] => 2007-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5296
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/952/07952398.pdf
[firstpage_image] =>[orig_patent_app_number] => 11741115
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/741115 | Bias circuit for common-mode and semiconductor process voltage and temperature optimization for a receiver assembly | Apr 26, 2007 | Issued |
Array
(
[id] => 4702501
[patent_doc_number] => 20080062023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-13
[patent_title] => 'LOW-PASS FILTER AND VOLTAGE-CURRENT CONVERSION CIRCUIT USED IN THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/739826
[patent_app_country] => US
[patent_app_date] => 2007-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1837
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0062/20080062023.pdf
[firstpage_image] =>[orig_patent_app_number] => 11739826
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/739826 | Low-pass filter and voltage-current conversion circuit used in the same | Apr 24, 2007 | Issued |
Array
(
[id] => 7492942
[patent_doc_number] => 08030990
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-04
[patent_title] => 'Measuring instrument in two-conductor technology'
[patent_app_type] => utility
[patent_app_number] => 12/298284
[patent_app_country] => US
[patent_app_date] => 2007-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3598
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/030/08030990.pdf
[firstpage_image] =>[orig_patent_app_number] => 12298284
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/298284 | Measuring instrument in two-conductor technology | Apr 22, 2007 | Issued |
Array
(
[id] => 4655338
[patent_doc_number] => 20080024199
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'Step-up booster circuit'
[patent_app_type] => utility
[patent_app_number] => 11/785308
[patent_app_country] => US
[patent_app_date] => 2007-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8074
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20080024199.pdf
[firstpage_image] =>[orig_patent_app_number] => 11785308
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/785308 | Step-up booster circuit | Apr 16, 2007 | Issued |
Array
(
[id] => 278561
[patent_doc_number] => 07557639
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-07
[patent_title] => 'Semiconductor device employing standby current reduction'
[patent_app_type] => utility
[patent_app_number] => 11/735843
[patent_app_country] => US
[patent_app_date] => 2007-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7300
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/557/07557639.pdf
[firstpage_image] =>[orig_patent_app_number] => 11735843
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/735843 | Semiconductor device employing standby current reduction | Apr 15, 2007 | Issued |
Array
(
[id] => 323201
[patent_doc_number] => 07518435
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-14
[patent_title] => 'Precharged power-down biasing circuit'
[patent_app_type] => utility
[patent_app_number] => 11/785216
[patent_app_country] => US
[patent_app_date] => 2007-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 2545
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/518/07518435.pdf
[firstpage_image] =>[orig_patent_app_number] => 11785216
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/785216 | Precharged power-down biasing circuit | Apr 15, 2007 | Issued |
Array
(
[id] => 4680294
[patent_doc_number] => 20080246520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-09
[patent_title] => 'DELAY-LOCKED LOOP (DLL) SYSTEM FOR DETERMINING FORWARD CLOCK PATH DELAY'
[patent_app_type] => utility
[patent_app_number] => 11/697858
[patent_app_country] => US
[patent_app_date] => 2007-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6273
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20080246520.pdf
[firstpage_image] =>[orig_patent_app_number] => 11697858
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/697858 | Delay-locked loop (DLL) system for determining forward clock path delay | Apr 8, 2007 | Issued |
Array
(
[id] => 5124006
[patent_doc_number] => 20070236277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-11
[patent_title] => 'Semiconductor integrated circuit device and substrate bias controlling method'
[patent_app_type] => utility
[patent_app_number] => 11/783432
[patent_app_country] => US
[patent_app_date] => 2007-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8819
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0236/20070236277.pdf
[firstpage_image] =>[orig_patent_app_number] => 11783432
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/783432 | Semiconductor integrated circuit device and substrate bias controlling method | Apr 8, 2007 | Issued |
Array
(
[id] => 5089513
[patent_doc_number] => 20070229152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'FILTER ADJUSTMENT CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/695204
[patent_app_country] => US
[patent_app_date] => 2007-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 9513
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0229/20070229152.pdf
[firstpage_image] =>[orig_patent_app_number] => 11695204
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/695204 | Filter adjustment circuit | Apr 1, 2007 | Issued |
Array
(
[id] => 4715987
[patent_doc_number] => 20080238509
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'BOUNDING A DUTY CYCLE USING A C-ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/694440
[patent_app_country] => US
[patent_app_date] => 2007-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4260
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0238/20080238509.pdf
[firstpage_image] =>[orig_patent_app_number] => 11694440
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/694440 | Bounding a duty cycle using a C-element | Mar 29, 2007 | Issued |
Array
(
[id] => 4716012
[patent_doc_number] => 20080238534
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'PHASE SHIFTING IN DLL/PLL'
[patent_app_type] => utility
[patent_app_number] => 11/691849
[patent_app_country] => US
[patent_app_date] => 2007-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11251
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0238/20080238534.pdf
[firstpage_image] =>[orig_patent_app_number] => 11691849
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/691849 | Phase shifting in DLL/PLL | Mar 26, 2007 | Issued |
Array
(
[id] => 4737683
[patent_doc_number] => 20080231335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'CIRCUIT TO REDUCE DUTY CYCLE DISTORTION'
[patent_app_type] => utility
[patent_app_number] => 11/688649
[patent_app_country] => US
[patent_app_date] => 2007-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3368
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20080231335.pdf
[firstpage_image] =>[orig_patent_app_number] => 11688649
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/688649 | CIRCUIT TO REDUCE DUTY CYCLE DISTORTION | Mar 19, 2007 | Abandoned |
Array
(
[id] => 289483
[patent_doc_number] => 07548100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-16
[patent_title] => 'Delay locked loop'
[patent_app_type] => utility
[patent_app_number] => 11/687396
[patent_app_country] => US
[patent_app_date] => 2007-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2595
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/548/07548100.pdf
[firstpage_image] =>[orig_patent_app_number] => 11687396
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/687396 | Delay locked loop | Mar 15, 2007 | Issued |
Array
(
[id] => 594384
[patent_doc_number] => 07436241
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-14
[patent_title] => 'Charge pump'
[patent_app_type] => utility
[patent_app_number] => 11/685162
[patent_app_country] => US
[patent_app_date] => 2007-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5661
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 499
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/436/07436241.pdf
[firstpage_image] =>[orig_patent_app_number] => 11685162
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/685162 | Charge pump | Mar 11, 2007 | Issued |
Array
(
[id] => 565991
[patent_doc_number] => 07471133
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-12-30
[patent_title] => 'Modulator circuit with linear and non-linear control'
[patent_app_type] => utility
[patent_app_number] => 11/683215
[patent_app_country] => US
[patent_app_date] => 2007-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5559
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/471/07471133.pdf
[firstpage_image] =>[orig_patent_app_number] => 11683215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/683215 | Modulator circuit with linear and non-linear control | Mar 6, 2007 | Issued |
Array
(
[id] => 594426
[patent_doc_number] => 07436246
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-14
[patent_title] => 'Pin number reduction circuit and methodology for mixed-signal IC, memory IC, and SOC'
[patent_app_type] => utility
[patent_app_number] => 11/711399
[patent_app_country] => US
[patent_app_date] => 2007-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2352
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/436/07436246.pdf
[firstpage_image] =>[orig_patent_app_number] => 11711399
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/711399 | Pin number reduction circuit and methodology for mixed-signal IC, memory IC, and SOC | Feb 25, 2007 | Issued |