Jeffery Shawn Zweizig

Array ( [id] => 4930871 [patent_doc_number] => 20080001646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Thermally stable semiconductor power device' [patent_app_type] => utility [patent_app_number] => 11/480041 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3306 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20080001646.pdf [firstpage_image] =>[orig_patent_app_number] => 11480041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5169371 [patent_doc_number] => 20070069802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Internal voltage generator' [patent_app_type] => utility [patent_app_number] => 11/478077 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2332 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069802.pdf [firstpage_image] =>[orig_patent_app_number] => 11478077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4930876 [patent_doc_number] => 20080001651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'N-CHANNEL NEGATIVE CHARGE PUMP' [patent_app_type] => utility [patent_app_number] => 11/479631 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4287 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20080001651.pdf [firstpage_image] =>[orig_patent_app_number] => 11479631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4930880 [patent_doc_number] => 20080001655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Programmable power gating circuit' [patent_app_type] => utility [patent_app_number] => 11/478394 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20080001655.pdf [firstpage_image] =>[orig_patent_app_number] => 11478394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4930872 [patent_doc_number] => 20080001647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Temperature stabilized integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/478954 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1197 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20080001647.pdf [firstpage_image] =>[orig_patent_app_number] => 11478954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 338531 [patent_doc_number] => 07504876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-17 [patent_title] => 'Substrate bias feedback scheme to reduce chip leakage power' [patent_app_type] => utility [patent_app_number] => 11/478006 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3512 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/504/07504876.pdf [firstpage_image] =>[orig_patent_app_number] => 11478006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4993451 [patent_doc_number] => 20070008796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Device and method for regulating the threshold voltage of a transistor' [patent_app_type] => utility [patent_app_number] => 11/477077 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5531 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20070008796.pdf [firstpage_image] =>[orig_patent_app_number] => 11477077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4992684 [patent_doc_number] => 20070008028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Over boosting prevention circuit' [patent_app_type] => utility [patent_app_number] => 11/475258 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6850 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20070008028.pdf [firstpage_image] =>[orig_patent_app_number] => 11475258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5197168 [patent_doc_number] => 20070296486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'VOLTAGE GENERATOR CIRCUIT, METHOD FOR PROVIDING AN OUTPUT VOLTAGE AND ELECTRONIC MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/473519 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7763 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20070296486.pdf [firstpage_image] =>[orig_patent_app_number] => 11473519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5234340 [patent_doc_number] => 20070126495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Precision reversed bandgap voltage reference circuits and method' [patent_app_type] => utility [patent_app_number] => 11/472791 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126495.pdf [firstpage_image] =>[orig_patent_app_number] => 11472791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5163566 [patent_doc_number] => 20070285150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Method and system for providing a charge pump very low voltage applications' [patent_app_type] => utility [patent_app_number] => 11/449052 [patent_app_country] => US [patent_app_date] => 2006-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5916 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20070285150.pdf [firstpage_image] =>[orig_patent_app_number] => 11449052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 585416 [patent_doc_number] => 07453314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Temperature-independent current source circuit' [patent_app_type] => utility [patent_app_number] => 11/447586 [patent_app_country] => US [patent_app_date] => 2006-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3014 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/453/07453314.pdf [firstpage_image] =>[orig_patent_app_number] => 11447586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 432825 [patent_doc_number] => 07265602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Voltage generating circuit with two resistor ladders' [patent_app_type] => utility [patent_app_number] => 11/433356 [patent_app_country] => US [patent_app_date] => 2006-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9292 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265602.pdf [firstpage_image] =>[orig_patent_app_number] => 11433356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 334843 [patent_doc_number] => 07508256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Integrated circuit with signal bus formed by cell abutment of logic cells' [patent_app_type] => utility [patent_app_number] => 11/433158 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4717 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/508/07508256.pdf [firstpage_image] =>[orig_patent_app_number] => 11433158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5146306 [patent_doc_number] => 20070046360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Electronic array having nodes and methods' [patent_app_type] => utility [patent_app_number] => 11/429401 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 13118 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20070046360.pdf [firstpage_image] =>[orig_patent_app_number] => 11429401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 513902 [patent_doc_number] => 07199639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Semiconductor device with level converter having signal-level shifting block and signal-level determination block' [patent_app_type] => utility [patent_app_number] => 11/410956 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 16810 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/199/07199639.pdf [firstpage_image] =>[orig_patent_app_number] => 11410956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5168805 [patent_doc_number] => 20070069236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Control circuit and method for driving a half-bridge circuit' [patent_app_type] => utility [patent_app_number] => 11/411199 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6830 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069236.pdf [firstpage_image] =>[orig_patent_app_number] => 11411199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 429176 [patent_doc_number] => 07268614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Low supply voltage bias circuit, semiconductor device, wafer and system including same, and method of generating a bias reference' [patent_app_type] => utility [patent_app_number] => 11/411286 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4754 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268614.pdf [firstpage_image] =>[orig_patent_app_number] => 11411286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5670747 [patent_doc_number] => 20060176101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/396543 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12886 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20060176101.pdf [firstpage_image] =>[orig_patent_app_number] => 11396543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5089491 [patent_doc_number] => 20070229130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'CHARGE PUMP CIRCUIT AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/278145 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2287 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20070229130.pdf [firstpage_image] =>[orig_patent_app_number] => 11278145 [rel_patent_id] =>[rel_patent_doc_number] =>)