
Jeffery Shawn Zweizig
Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2816, 2849, 2842, 2504 |
| Total Applications | 2640 |
| Issued Applications | 2460 |
| Pending Applications | 67 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 409157
[patent_doc_number] => 07286004
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-23
[patent_title] => 'Current source circuit'
[patent_app_type] => utility
[patent_app_number] => 11/253613
[patent_app_country] => US
[patent_app_date] => 2005-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4931
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/286/07286004.pdf
[firstpage_image] =>[orig_patent_app_number] => 11253613
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/253613 | Current source circuit | Oct 19, 2005 | Issued |
Array
(
[id] => 432828
[patent_doc_number] => 07265605
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-09-04
[patent_title] => 'Supply regulator for memory cells with suspend mode capability for low power applications'
[patent_app_type] => utility
[patent_app_number] => 11/252504
[patent_app_country] => US
[patent_app_date] => 2005-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6273
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/265/07265605.pdf
[firstpage_image] =>[orig_patent_app_number] => 11252504
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/252504 | Supply regulator for memory cells with suspend mode capability for low power applications | Oct 17, 2005 | Issued |
Array
(
[id] => 5646495
[patent_doc_number] => 20060132227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'MOS type semiconductor integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 11/251824
[patent_app_country] => US
[patent_app_date] => 2005-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6677
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0132/20060132227.pdf
[firstpage_image] =>[orig_patent_app_number] => 11251824
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/251824 | MOS type semiconductor integrated circuit device | Oct 17, 2005 | Issued |
Array
(
[id] => 474500
[patent_doc_number] => 07230472
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-12
[patent_title] => 'Base current cancellation for bipolar junction transistor current summing bias voltage generator'
[patent_app_type] => utility
[patent_app_number] => 11/248892
[patent_app_country] => US
[patent_app_date] => 2005-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5203
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/230/07230472.pdf
[firstpage_image] =>[orig_patent_app_number] => 11248892
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/248892 | Base current cancellation for bipolar junction transistor current summing bias voltage generator | Oct 10, 2005 | Issued |
Array
(
[id] => 480844
[patent_doc_number] => 07224207
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-29
[patent_title] => 'Charge pump system with smooth voltage output'
[patent_app_type] => utility
[patent_app_number] => 11/231035
[patent_app_country] => US
[patent_app_date] => 2005-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3794
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/224/07224207.pdf
[firstpage_image] =>[orig_patent_app_number] => 11231035
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/231035 | Charge pump system with smooth voltage output | Sep 19, 2005 | Issued |
Array
(
[id] => 660111
[patent_doc_number] => 07106109
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Biasing circuit and voltage control oscillator thereof'
[patent_app_type] => utility
[patent_app_number] => 11/162654
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3701
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/106/07106109.pdf
[firstpage_image] =>[orig_patent_app_number] => 11162654
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/162654 | Biasing circuit and voltage control oscillator thereof | Sep 18, 2005 | Issued |
Array
(
[id] => 513955
[patent_doc_number] => 07199649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-03
[patent_title] => 'Switching power supply'
[patent_app_type] => utility
[patent_app_number] => 11/227338
[patent_app_country] => US
[patent_app_date] => 2005-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2108
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/199/07199649.pdf
[firstpage_image] =>[orig_patent_app_number] => 11227338
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/227338 | Switching power supply | Sep 14, 2005 | Issued |
Array
(
[id] => 465915
[patent_doc_number] => 07239195
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-07-03
[patent_title] => 'Active power supply rejection using negative current generation loop feedback'
[patent_app_type] => utility
[patent_app_number] => 11/227363
[patent_app_country] => US
[patent_app_date] => 2005-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 3137
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/239/07239195.pdf
[firstpage_image] =>[orig_patent_app_number] => 11227363
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/227363 | Active power supply rejection using negative current generation loop feedback | Sep 14, 2005 | Issued |
Array
(
[id] => 5724688
[patent_doc_number] => 20060055448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Voltage generator'
[patent_app_type] => utility
[patent_app_number] => 11/224142
[patent_app_country] => US
[patent_app_date] => 2005-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 13648
[patent_no_of_claims] => 7
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0055/20060055448.pdf
[firstpage_image] =>[orig_patent_app_number] => 11224142
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/224142 | Voltage generator | Sep 12, 2005 | Abandoned |
Array
(
[id] => 4913532
[patent_doc_number] => 20080094131
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'Bias Circuits'
[patent_app_type] => utility
[patent_app_number] => 11/575301
[patent_app_country] => US
[patent_app_date] => 2005-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2783
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20080094131.pdf
[firstpage_image] =>[orig_patent_app_number] => 11575301
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/575301 | Bias circuits | Sep 12, 2005 | Issued |
Array
(
[id] => 5736536
[patent_doc_number] => 20060006926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Potential detector and semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/223959
[patent_app_country] => US
[patent_app_date] => 2005-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 7961
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20060006926.pdf
[firstpage_image] =>[orig_patent_app_number] => 11223959
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/223959 | Potential detector and semiconductor integrated circuit | Sep 12, 2005 | Issued |
Array
(
[id] => 103542
[patent_doc_number] => 07728656
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-01
[patent_title] => 'Signal input circuit'
[patent_app_type] => utility
[patent_app_number] => 11/663937
[patent_app_country] => US
[patent_app_date] => 2005-09-09
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/728/07728656.pdf
[firstpage_image] =>[orig_patent_app_number] => 11663937
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/663937 | Signal input circuit | Sep 8, 2005 | Issued |
Array
(
[id] => 5741625
[patent_doc_number] => 20060087348
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Semiconductor device for driving a load'
[patent_app_type] => utility
[patent_app_number] => 11/220529
[patent_app_country] => US
[patent_app_date] => 2005-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2258
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[pdf_file] => publications/A1/0087/20060087348.pdf
[firstpage_image] =>[orig_patent_app_number] => 11220529
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/220529 | Semiconductor device for driving a load | Sep 7, 2005 | Issued |
Array
(
[id] => 477201
[patent_doc_number] => 07227401
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'Resistorless bias current generation circuit'
[patent_app_type] => utility
[patent_app_number] => 11/225587
[patent_app_country] => US
[patent_app_date] => 2005-08-31
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/227/07227401.pdf
[firstpage_image] =>[orig_patent_app_number] => 11225587
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/225587 | Resistorless bias current generation circuit | Aug 30, 2005 | Issued |
Array
(
[id] => 415771
[patent_doc_number] => 07279957
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-09
[patent_title] => 'Charge pump for generating arbitrary voltage levels'
[patent_app_type] => utility
[patent_app_number] => 11/162147
[patent_app_country] => US
[patent_app_date] => 2005-08-30
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[pdf_file] => patents/07/279/07279957.pdf
[firstpage_image] =>[orig_patent_app_number] => 11162147
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/162147 | Charge pump for generating arbitrary voltage levels | Aug 29, 2005 | Issued |
Array
(
[id] => 5899067
[patent_doc_number] => 20060044046
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Gate drive circuit with negative offset'
[patent_app_type] => utility
[patent_app_number] => 11/212259
[patent_app_country] => US
[patent_app_date] => 2005-08-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0044/20060044046.pdf
[firstpage_image] =>[orig_patent_app_number] => 11212259
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/212259 | Gate drive circuit with negative offset | Aug 25, 2005 | Issued |
Array
(
[id] => 521439
[patent_doc_number] => 07193453
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-20
[patent_title] => 'Dual loop voltage regulation circuit of power supply chip'
[patent_app_type] => utility
[patent_app_number] => 11/208651
[patent_app_country] => US
[patent_app_date] => 2005-08-23
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/193/07193453.pdf
[firstpage_image] =>[orig_patent_app_number] => 11208651
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/208651 | Dual loop voltage regulation circuit of power supply chip | Aug 22, 2005 | Issued |
Array
(
[id] => 496905
[patent_doc_number] => 07212060
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-05-01
[patent_title] => 'Ground bounce protection circuit for a test mode pin'
[patent_app_type] => utility
[patent_app_number] => 11/210136
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[pdf_file] => patents/07/212/07212060.pdf
[firstpage_image] =>[orig_patent_app_number] => 11210136
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/210136 | Ground bounce protection circuit for a test mode pin | Aug 22, 2005 | Issued |
Array
(
[id] => 5718930
[patent_doc_number] => 20060071703
[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'On-chip voltage regulator'
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[firstpage_image] =>[orig_patent_app_number] => 11209351
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/209351 | On-chip voltage regulator | Aug 21, 2005 | Issued |
Array
(
[id] => 692435
[patent_doc_number] => 07075358
[patent_country] => US
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[patent_title] => 'Base current compensation for a bipolar transistor current mirror circuit'
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[pdf_file] => patents/07/075/07075358.pdf
[firstpage_image] =>[orig_patent_app_number] => 11204481
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/204481 | Base current compensation for a bipolar transistor current mirror circuit | Aug 14, 2005 | Issued |