
Jeffery Shawn Zweizig
Examiner (ID: 3642, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2816, 2849, 2842, 2504 |
| Total Applications | 2640 |
| Issued Applications | 2460 |
| Pending Applications | 67 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7140987
[patent_doc_number] => 20050116766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Bias voltage generator circuit'
[patent_app_type] => utility
[patent_app_number] => 10/999179
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Array
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[patent_issue_date] => 2007-02-27
[patent_title] => 'Circuit and method for switching an electrical load on after a delay'
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[patent_title] => 'Systems and methods for minimizing static leakage of an integrated circuit'
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Array
(
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/991301 | Ring oscillator for digital multilevel non-volatile memory | Nov 15, 2004 | Issued |
Array
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[id] => 5774814
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[patent_title] => 'Temperature compensated FET constant current source'
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Array
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[id] => 429172
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[patent_title] => 'Low-voltage CMOS switch with novel clock boosting scheme'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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