Search

Jeffery Shawn Zweizig

Examiner (ID: 5312, Phone: (571)272-1758 , Office: P/2842 )

Most Active Art Unit
2816
Art Unit(s)
2816, 2842, 2849, 2504
Total Applications
2641
Issued Applications
2460
Pending Applications
70
Abandoned Applications
136

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5351453 [patent_doc_number] => 20090006814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Immediate and Displacement Extraction and Decode Mechanism' [patent_app_type] => utility [patent_app_number] => 11/768417 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006814.pdf [firstpage_image] =>[orig_patent_app_number] => 11768417 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768417
Immediate and displacement extraction and decode mechanism Jun 25, 2007 Issued
Array ( [id] => 4804730 [patent_doc_number] => 20080016319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'PROCESSOR ARCHITECTURE, FOR INSTANCE FOR MULTIMEDIA APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 11/768481 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4860 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016319.pdf [firstpage_image] =>[orig_patent_app_number] => 11768481 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768481
Processor architecture with processing clusters providing vector and scalar data processing capability Jun 25, 2007 Issued
Array ( [id] => 4590961 [patent_doc_number] => 07827391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method and apparatus for single-stepping coherence events in a multiprocessor system under software control' [patent_app_type] => utility [patent_app_number] => 11/768857 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5193 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827391.pdf [firstpage_image] =>[orig_patent_app_number] => 11768857 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/768857
Method and apparatus for single-stepping coherence events in a multiprocessor system under software control Jun 25, 2007 Issued
Array ( [id] => 4589863 [patent_doc_number] => 07831818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Exception-based timer control' [patent_app_type] => utility [patent_app_number] => 11/765891 [patent_app_country] => US [patent_app_date] => 2007-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7064 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831818.pdf [firstpage_image] =>[orig_patent_app_number] => 11765891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765891
Exception-based timer control Jun 19, 2007 Issued
Array ( [id] => 4854535 [patent_doc_number] => 20080320278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'SYSTEM AND METHOD FOR EFFICIENT DATA TRANSMISSION IN A MULTI-PROCESSOR ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 11/765372 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4259 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320278.pdf [firstpage_image] =>[orig_patent_app_number] => 11765372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765372
System and method for efficient data transmission in a multi-processor environment Jun 18, 2007 Issued
Array ( [id] => 4754798 [patent_doc_number] => 20080162874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/765421 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12769 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162874.pdf [firstpage_image] =>[orig_patent_app_number] => 11765421 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/765421
PARALLEL DATA PROCESSING APPARATUS Jun 18, 2007 Abandoned
Array ( [id] => 5212100 [patent_doc_number] => 20070250684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Central processing unit having a micro-code engine' [patent_app_type] => utility [patent_app_number] => 11/790918 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5672 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20070250684.pdf [firstpage_image] =>[orig_patent_app_number] => 11790918 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/790918
Central processing unit having a micro-code engine Apr 29, 2007 Abandoned
Array ( [id] => 106831 [patent_doc_number] => 07730280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Methods and apparatus for independent processor node operations in a SIMD array processor' [patent_app_type] => utility [patent_app_number] => 11/736814 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4717 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730280.pdf [firstpage_image] =>[orig_patent_app_number] => 11736814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/736814
Methods and apparatus for independent processor node operations in a SIMD array processor Apr 17, 2007 Issued
Array ( [id] => 4889055 [patent_doc_number] => 20080263387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'FAULT RECOVERY ON A PARALLEL COMPUTER SYSTEM WITH A TORUS NETWORK' [patent_app_type] => utility [patent_app_number] => 11/736923 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5197 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263387.pdf [firstpage_image] =>[orig_patent_app_number] => 11736923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/736923
Fault recovery on a parallel computer system with a torus network Apr 17, 2007 Issued
Array ( [id] => 4888999 [patent_doc_number] => 20080263331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Universal Register Rename Mechanism for Instructions with Multiple Targets in a Microprocessor' [patent_app_type] => utility [patent_app_number] => 11/736855 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263331.pdf [firstpage_image] =>[orig_patent_app_number] => 11736855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/736855
Universal register rename mechanism for instructions with multiple targets in a microprocessor Apr 17, 2007 Issued
Array ( [id] => 4888989 [patent_doc_number] => 20080263321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Universal Register Rename Mechanism for Targets of Different Instruction Types in a Microprocessor' [patent_app_type] => utility [patent_app_number] => 11/736844 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8689 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263321.pdf [firstpage_image] =>[orig_patent_app_number] => 11736844 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/736844
Universal register rename mechanism for targets of different instruction types in a microprocessor Apr 17, 2007 Issued
Array ( [id] => 156218 [patent_doc_number] => 07681020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Context switching and synchronization' [patent_app_type] => utility [patent_app_number] => 11/736936 [patent_app_country] => US [patent_app_date] => 2007-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 12085 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681020.pdf [firstpage_image] =>[orig_patent_app_number] => 11736936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/736936
Context switching and synchronization Apr 17, 2007 Issued
Array ( [id] => 4665472 [patent_doc_number] => 20080256379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'Clock architecture for multi-processor systems' [patent_app_type] => utility [patent_app_number] => 11/786125 [patent_app_country] => US [patent_app_date] => 2007-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256379.pdf [firstpage_image] =>[orig_patent_app_number] => 11786125 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/786125
Clock architecture for multi-processor systems Apr 10, 2007 Issued
Array ( [id] => 126754 [patent_doc_number] => 07711933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-04 [patent_title] => 'Exploiting unused configuration memory cells' [patent_app_type] => utility [patent_app_number] => 11/784848 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2913 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/711/07711933.pdf [firstpage_image] =>[orig_patent_app_number] => 11784848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/784848
Exploiting unused configuration memory cells Apr 8, 2007 Issued
Array ( [id] => 5248892 [patent_doc_number] => 20070245126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Program counter of microcontroller and control method thereof' [patent_app_type] => utility [patent_app_number] => 11/783415 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1420 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245126.pdf [firstpage_image] =>[orig_patent_app_number] => 11783415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/783415
Program counter of microcontroller and control method thereof Apr 8, 2007 Abandoned
Array ( [id] => 4825951 [patent_doc_number] => 20080229075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'MICROCONTROLLER WITH LOW-COST DIGITAL SIGNAL PROCESSING EXTENSIONS' [patent_app_type] => utility [patent_app_number] => 11/687264 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9717 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229075.pdf [firstpage_image] =>[orig_patent_app_number] => 11687264 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/687264
Microcontroller with low-cost digital signal processing extensions Mar 15, 2007 Issued
Array ( [id] => 4572575 [patent_doc_number] => 07962717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Message routing scheme' [patent_app_type] => utility [patent_app_number] => 11/717621 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5612 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962717.pdf [firstpage_image] =>[orig_patent_app_number] => 11717621 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717621
Message routing scheme Mar 13, 2007 Issued
Array ( [id] => 4825944 [patent_doc_number] => 20080229069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'System, Method And Software To Preload Instructions From An Instruction Set Other Than One Currently Executing' [patent_app_type] => utility [patent_app_number] => 11/685850 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3530 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229069.pdf [firstpage_image] =>[orig_patent_app_number] => 11685850 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685850
System, method and software to preload instructions from an instruction set other than one currently executing Mar 13, 2007 Issued
Array ( [id] => 4825961 [patent_doc_number] => 20080229083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Processor instruction set' [patent_app_type] => utility [patent_app_number] => 11/717616 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10463 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229083.pdf [firstpage_image] =>[orig_patent_app_number] => 11717616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717616
Processor instruction set for controlling threads to respond to events Mar 13, 2007 Issued
Array ( [id] => 7690019 [patent_doc_number] => 20070234014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Processor apparatus for executing instructions with local slack prediction of instructions and processing method therefor' [patent_app_type] => utility [patent_app_number] => 11/717063 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 46325 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234014.pdf [firstpage_image] =>[orig_patent_app_number] => 11717063 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717063
Processor apparatus for executing instructions with local slack prediction of instructions and processing method therefor Mar 12, 2007 Abandoned
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