
Jeffery Shawn Zweizig
Examiner (ID: 12123, Phone: (571)272-1758 , Office: P/2842 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2849, 2816, 2842, 2504 |
| Total Applications | 2645 |
| Issued Applications | 2451 |
| Pending Applications | 87 |
| Abandoned Applications | 136 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 630917
[patent_doc_number] => 07132878
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-07
[patent_title] => 'Charge pump current source'
[patent_app_type] => utility
[patent_app_number] => 10/991591
[patent_app_country] => US
[patent_app_date] => 2004-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1974
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/132/07132878.pdf
[firstpage_image] =>[orig_patent_app_number] => 10991591
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/991591 | Charge pump current source | Nov 17, 2004 | Issued |
Array
(
[id] => 944470
[patent_doc_number] => 06967524
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-22
[patent_title] => 'High voltage generation and regulation system for digital multilevel nonvolatile memory'
[patent_app_type] => utility
[patent_app_number] => 10/990786
[patent_app_country] => US
[patent_app_date] => 2004-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 9425
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/967/06967524.pdf
[firstpage_image] =>[orig_patent_app_number] => 10990786
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/990786 | High voltage generation and regulation system for digital multilevel nonvolatile memory | Nov 15, 2004 | Issued |
Array
(
[id] => 6989184
[patent_doc_number] => 20050088221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'High voltage generation and regulation system for digital multilevel nonvolatile memory'
[patent_app_type] => utility
[patent_app_number] => 10/991301
[patent_app_country] => US
[patent_app_date] => 2004-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9374
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20050088221.pdf
[firstpage_image] =>[orig_patent_app_number] => 10991301
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/991301 | Ring oscillator for digital multilevel non-volatile memory | Nov 15, 2004 | Issued |
Array
(
[id] => 5774814
[patent_doc_number] => 20060103454
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-18
[patent_title] => 'Temperature compensated FET constant current source'
[patent_app_type] => utility
[patent_app_number] => 10/988071
[patent_app_country] => US
[patent_app_date] => 2004-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1667
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0103/20060103454.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988071
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988071 | Temperature compensated FET constant current source | Nov 12, 2004 | Issued |
Array
(
[id] => 429172
[patent_doc_number] => 07268610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Low-voltage CMOS switch with novel clock boosting scheme'
[patent_app_type] => utility
[patent_app_number] => 10/986630
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5382
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/268/07268610.pdf
[firstpage_image] =>[orig_patent_app_number] => 10986630
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/986630 | Low-voltage CMOS switch with novel clock boosting scheme | Nov 11, 2004 | Issued |
Array
(
[id] => 6903829
[patent_doc_number] => 20050099224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Selecting a reference voltage suitable to load functionality'
[patent_app_type] => utility
[patent_app_number] => 10/987695
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3345
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20050099224.pdf
[firstpage_image] =>[orig_patent_app_number] => 10987695
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/987695 | Selecting a reference voltage suitable to load functionality | Nov 11, 2004 | Issued |
Array
(
[id] => 6903828
[patent_doc_number] => 20050099223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Integration and terminal arrangement of parallel monitor circuits'
[patent_app_type] => utility
[patent_app_number] => 10/982886
[patent_app_country] => US
[patent_app_date] => 2004-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4845
[patent_no_of_claims] => 75
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20050099223.pdf
[firstpage_image] =>[orig_patent_app_number] => 10982886
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/982886 | Integration and terminal arrangement of parallel monitor circuits | Nov 7, 2004 | Issued |
Array
(
[id] => 542158
[patent_doc_number] => 07176748
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Charge pump circuit with a brief settling time and high output voltage regulation precision'
[patent_app_type] => utility
[patent_app_number] => 10/982528
[patent_app_country] => US
[patent_app_date] => 2004-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3252
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/176/07176748.pdf
[firstpage_image] =>[orig_patent_app_number] => 10982528
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/982528 | Charge pump circuit with a brief settling time and high output voltage regulation precision | Nov 4, 2004 | Issued |
Array
(
[id] => 7155584
[patent_doc_number] => 20050083104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Method of operation in a system having a memory device having an adjustable output voltage setting'
[patent_app_type] => utility
[patent_app_number] => 10/981808
[patent_app_country] => US
[patent_app_date] => 2004-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6329
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20050083104.pdf
[firstpage_image] =>[orig_patent_app_number] => 10981808
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/981808 | Method of operation in a system having a memory device having an adjustable output voltage setting | Nov 4, 2004 | Issued |
Array
(
[id] => 660146
[patent_doc_number] => 07106128
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Processor apparatus with body bias circuitry to delay thermal throttling'
[patent_app_type] => utility
[patent_app_number] => 10/982266
[patent_app_country] => US
[patent_app_date] => 2004-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5008
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/106/07106128.pdf
[firstpage_image] =>[orig_patent_app_number] => 10982266
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/982266 | Processor apparatus with body bias circuitry to delay thermal throttling | Nov 2, 2004 | Issued |
Array
(
[id] => 5805579
[patent_doc_number] => 20060091932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Pass transistors with minimized capacitive loading'
[patent_app_type] => utility
[patent_app_number] => 10/980021
[patent_app_country] => US
[patent_app_date] => 2004-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3522
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0091/20060091932.pdf
[firstpage_image] =>[orig_patent_app_number] => 10980021
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/980021 | Pass transistors with minimized capacitive loading | Nov 1, 2004 | Issued |
Array
(
[id] => 7170038
[patent_doc_number] => 20050122159
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Fuse circuit with controlled fuse burn out and method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/968171
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2977
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20050122159.pdf
[firstpage_image] =>[orig_patent_app_number] => 10968171
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/968171 | Fuse circuit with controlled fuse burn out and method thereof | Oct 19, 2004 | Issued |
Array
(
[id] => 394497
[patent_doc_number] => 07298198
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-20
[patent_title] => 'Charge pump'
[patent_app_type] => utility
[patent_app_number] => 10/575480
[patent_app_country] => US
[patent_app_date] => 2004-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 6250
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/298/07298198.pdf
[firstpage_image] =>[orig_patent_app_number] => 10575480
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/575480 | Charge pump | Oct 14, 2004 | Issued |
Array
(
[id] => 6975953
[patent_doc_number] => 20050285668
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Semiconductor integrated circuit and designing method for same'
[patent_app_type] => utility
[patent_app_number] => 10/964638
[patent_app_country] => US
[patent_app_date] => 2004-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4110
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0285/20050285668.pdf
[firstpage_image] =>[orig_patent_app_number] => 10964638
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/964638 | Semiconductor integrated circuit and designing method for same | Oct 14, 2004 | Issued |
Array
(
[id] => 7239190
[patent_doc_number] => 20050140400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Common voltage source integrated circuit for liquid crystal display device'
[patent_app_type] => utility
[patent_app_number] => 10/963576
[patent_app_country] => US
[patent_app_date] => 2004-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6942
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20050140400.pdf
[firstpage_image] =>[orig_patent_app_number] => 10963576
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/963576 | Common voltage source integrated circuit for liquid crystal display device | Oct 13, 2004 | Issued |
Array
(
[id] => 7102860
[patent_doc_number] => 20050105586
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Temperature sensor circuit'
[patent_app_type] => utility
[patent_app_number] => 10/965125
[patent_app_country] => US
[patent_app_date] => 2004-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1681
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0105/20050105586.pdf
[firstpage_image] =>[orig_patent_app_number] => 10965125
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/965125 | Temperature sensor circuit | Oct 13, 2004 | Issued |
Array
(
[id] => 7602990
[patent_doc_number] => 07236044
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-26
[patent_title] => 'Apparatus and method for adjusting the substrate impedance of a MOS transistor'
[patent_app_type] => utility
[patent_app_number] => 10/965683
[patent_app_country] => US
[patent_app_date] => 2004-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3179
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/236/07236044.pdf
[firstpage_image] =>[orig_patent_app_number] => 10965683
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/965683 | Apparatus and method for adjusting the substrate impedance of a MOS transistor | Oct 12, 2004 | Issued |
Array
(
[id] => 630916
[patent_doc_number] => 07132877
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-07
[patent_title] => 'Radiation tolerant solid-state relay'
[patent_app_type] => utility
[patent_app_number] => 10/963957
[patent_app_country] => US
[patent_app_date] => 2004-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2571
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/132/07132877.pdf
[firstpage_image] =>[orig_patent_app_number] => 10963957
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/963957 | Radiation tolerant solid-state relay | Oct 11, 2004 | Issued |
Array
(
[id] => 5708517
[patent_doc_number] => 20060049861
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Method and system for ensuring the assertion order of signals in a chip independent of physical layout'
[patent_app_type] => utility
[patent_app_number] => 10/961015
[patent_app_country] => US
[patent_app_date] => 2004-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4679
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20060049861.pdf
[firstpage_image] =>[orig_patent_app_number] => 10961015
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/961015 | Method and system for ensuring the assertion order of signals in a chip independent of physical layout | Oct 7, 2004 | Issued |
Array
(
[id] => 656249
[patent_doc_number] => 07109782
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-19
[patent_title] => 'Well bias voltage generator'
[patent_app_type] => utility
[patent_app_number] => 10/958831
[patent_app_country] => US
[patent_app_date] => 2004-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4112
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/109/07109782.pdf
[firstpage_image] =>[orig_patent_app_number] => 10958831
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/958831 | Well bias voltage generator | Oct 4, 2004 | Issued |