Jeffery Shawn Zweizig

Array ( [id] => 1000025 [patent_doc_number] => 06911862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Ultra-low current band-gap reference' [patent_app_type] => utility [patent_app_number] => 10/924186 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3743 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/911/06911862.pdf [firstpage_image] =>[orig_patent_app_number] => 10924186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7193079 [patent_doc_number] => 20050040879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/921998 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6215 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20050040879.pdf [firstpage_image] =>[orig_patent_app_number] => 10921998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 643189 [patent_doc_number] => 07123076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/921290 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5812 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123076.pdf [firstpage_image] =>[orig_patent_app_number] => 10921290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 458362 [patent_doc_number] => 07245173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Method to reduce integrated circuit power consumption by using differential signaling within the device' [patent_app_type] => utility [patent_app_number] => 10/919137 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2378 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245173.pdf [firstpage_image] =>[orig_patent_app_number] => 10919137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 454303 [patent_doc_number] => 07248093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Bipolar bootstrap top switch gate drive for half-bridge semiconductor power topologies' [patent_app_type] => utility [patent_app_number] => 10/710958 [patent_app_country] => US [patent_app_date] => 2004-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3249 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248093.pdf [firstpage_image] =>[orig_patent_app_number] => 10710958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 253264 [patent_doc_number] => 07579900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Operation and circuitry of a power conversion and control circuit' [patent_app_type] => utility [patent_app_number] => 10/567396 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3767 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/579/07579900.pdf [firstpage_image] =>[orig_patent_app_number] => 10567396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7032174 [patent_doc_number] => 20050030683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Self-reparable device to generate a high voltage, and method for repairing a device to generate a high voltage' [patent_app_type] => utility [patent_app_number] => 10/911409 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6991 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20050030683.pdf [firstpage_image] =>[orig_patent_app_number] => 10911409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5818430 [patent_doc_number] => 20060022743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'On chip word line voltage with PVT tracking for memory embedded in logic process' [patent_app_type] => utility [patent_app_number] => 10/909729 [patent_app_country] => US [patent_app_date] => 2004-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2633 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022743.pdf [firstpage_image] =>[orig_patent_app_number] => 10909729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 549373 [patent_doc_number] => 07167039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Memory device having an adjustable voltage swing setting' [patent_app_type] => utility [patent_app_number] => 10/890972 [patent_app_country] => US [patent_app_date] => 2004-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6495 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167039.pdf [firstpage_image] =>[orig_patent_app_number] => 10890972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5736538 [patent_doc_number] => 20060006928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Voltage generating circuit with two resistor ladders' [patent_app_type] => utility [patent_app_number] => 10/885776 [patent_app_country] => US [patent_app_date] => 2004-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9239 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20060006928.pdf [firstpage_image] =>[orig_patent_app_number] => 10885776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 613342 [patent_doc_number] => 07148742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Power supply voltage detection circuitry and methods for use of the same' [patent_app_type] => utility [patent_app_number] => 10/886771 [patent_app_country] => US [patent_app_date] => 2004-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4874 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148742.pdf [firstpage_image] =>[orig_patent_app_number] => 10886771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 635009 [patent_doc_number] => 07129770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'High voltage tracking bias voltage' [patent_app_type] => utility [patent_app_number] => 10/882512 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6846 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129770.pdf [firstpage_image] =>[orig_patent_app_number] => 10882512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7604780 [patent_doc_number] => 07116151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Stress tolerant high voltage back-to-back switch' [patent_app_type] => utility [patent_app_number] => 10/883361 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3595 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/116/07116151.pdf [firstpage_image] =>[orig_patent_app_number] => 10883361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5892937 [patent_doc_number] => 20060001475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Class-AB beta helper to reduce effects of mirror perturbation' [patent_app_type] => utility [patent_app_number] => 10/881284 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1090 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20060001475.pdf [firstpage_image] =>[orig_patent_app_number] => 10881284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7192750 [patent_doc_number] => 20050040804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Plate voltage generation circuit capable controlling dead band' [patent_app_type] => utility [patent_app_number] => 10/878486 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9724 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20050040804.pdf [firstpage_image] =>[orig_patent_app_number] => 10878486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 760084 [patent_doc_number] => 07015743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Circuit of redundancy IO fuse in semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/879434 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2677 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015743.pdf [firstpage_image] =>[orig_patent_app_number] => 10879434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6975951 [patent_doc_number] => 20050285666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Voltage reference generator circuit subtracting CTAT current from PTAT current' [patent_app_type] => utility [patent_app_number] => 10/877288 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3671 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285666.pdf [firstpage_image] =>[orig_patent_app_number] => 10877288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7606991 [patent_doc_number] => 07098725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Multi stage voltage pump circuit' [patent_app_type] => utility [patent_app_number] => 10/874240 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3963 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098725.pdf [firstpage_image] =>[orig_patent_app_number] => 10874240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 726429 [patent_doc_number] => 07046079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Circuit for generating a reference voltage' [patent_app_type] => utility [patent_app_number] => 10/710124 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3368 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046079.pdf [firstpage_image] =>[orig_patent_app_number] => 10710124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 991229 [patent_doc_number] => 06919756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Method and circuit for adjusting a voltage upon detection of a command applied to an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/873512 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5959 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919756.pdf [firstpage_image] =>[orig_patent_app_number] => 10873512 [rel_patent_id] =>[rel_patent_doc_number] =>)